include/configs/ve8313.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  *
   5  * (C) Copyright 2010
   6  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   7  */
   8 /*
   9  * ve8313 board configuration file
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300             1
  19
  20 #define CONFIG_PCI_INDIRECT_BRIDGE 1
  21 #define CONFIG_FSL_ELBC         1
  22
  23 /*
  24  * On-board devices
  25  *
  26  */
  27 #define CONFIG_SYS_IMMR         0xE0000000
  28
  29 #define CONFIG_SYS_MEMTEST_START        0x00001000
  30 #define CONFIG_SYS_MEMTEST_END          0x07000000
  31
  32 #define CONFIG_SYS_ACR_PIPE_DEP         3       /* Arbiter pipeline depth */
  33 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count */
  34
  35 /*
  36  * Device configurations
  37  */
  38
  39 /*
  40  * DDR Setup
  41  */
  42 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  43 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  44 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  45
  46 /*
  47  * Manually set up DDR parameters, as this board does not
  48  * have the SPD connected to I2C.
  49  */
  50 #define CONFIG_SYS_DDR_SIZE     128     /* MB */
  51 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  52                                 | CSCONFIG_AP \
  53                                 | CSCONFIG_ODT_RD_NEVER \
  54                                 | CSCONFIG_ODT_WR_ALL \
  55                                 | CSCONFIG_ROW_BIT_13 \
  56                                 | CSCONFIG_COL_BIT_10)
  57                                 /* 0x80840102 */
  58
  59 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  60 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  61                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  62                                 | (3 << TIMING_CFG0_RRT_SHIFT) \
  63                                 | (2 << TIMING_CFG0_WWT_SHIFT) \
  64                                 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  65                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  66                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  67                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  68                                 /* 0x0e720802 */
  69 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  70                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  71                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  72                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  73                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
  74                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  75                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  76                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  77                                 /* 0x26256222 */
  78 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  79                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
  80                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  81                                 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  82                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  83                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  84                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  85                                 /* 0x029028c7 */
  86 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
  87                                 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  88                                 /* 0x03202000 */
  89 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
  90                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  91                                 | SDRAM_CFG_DBW_32)
  92                                 /* 0x43080000 */
  93 #define CONFIG_SYS_SDRAM_CFG2   0x00401000
  94 #define CONFIG_SYS_DDR_MODE     ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
  95                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  96                                 /* 0x44400232 */
  97 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
  98
  99 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 100                                 /*0x02000000*/
 101 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 102                                 | DDRCDR_PZ_NOMZ \
 103                                 | DDRCDR_NZ_NOMZ \
 104                                 | DDRCDR_M_ODR)
 105                                 /* 0x73000002 */
 106
 107 /*
 108  * FLASH on the Local Bus
 109  */
 110 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 111 #define CONFIG_SYS_FLASH_SIZE           32      /* size in MB */
 112 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 113
 114 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 115 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 116
 117 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 118 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per dev */
 119
 120 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 121 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 122
 123 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 124
 125 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 126 #define CONFIG_SYS_RAMBOOT
 127 #endif
 128
 129 #define CONFIG_SYS_INIT_RAM_LOCK        1
 130 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
 131 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 132
 133 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 134                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 135 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 136
 137 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 138 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)
 139 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 140
 141 /*
 142  * Local Bus LCRR and LBCR regs
 143  */
 144 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_3
 145 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_2
 146
 147 #define CONFIG_SYS_LBC_LBCR     0x00040000
 148
 149 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 150
 151 /*
 152  * NAND settings
 153  */
 154 #define CONFIG_SYS_NAND_BASE            0x61000000
 155 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 156 #define CONFIG_NAND_FSL_ELBC 1
 157 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 158
 159
 160 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
 161                                         | BR_PS_16      /* 16 bit */ \
 162                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 163                                         | BR_V)         /* valid */
 164 #define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \
 165                                         | OR_GPCM_CSNT \
 166                                         | OR_GPCM_ACS_DIV4 \
 167                                         | OR_GPCM_SCY_5 \
 168                                         | OR_GPCM_TRLX_SET \
 169                                         | OR_GPCM_EAD)
 170                                         /* 0xfe000c55 */
 171
 172 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
 173                                         | BR_PS_8               \
 174                                         | BR_DECC_CHK_GEN       \
 175                                         | BR_MS_FCM             \
 176                                         | BR_V) /* valid */
 177                                         /* 0x61000c21 */
 178 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
 179                                         | OR_FCM_BCTLD \
 180                                         | OR_FCM_CHT \
 181                                         | OR_FCM_SCY_2 \
 182                                         | OR_FCM_RST \
 183                                         | OR_FCM_TRLX) /* 0xffff90ac */
 184
 185 /* Still needed for spl_minimal.c */
 186 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 187 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 188
 189 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 190 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 191
 192 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 193 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 194
 195 /* CS2 NvRAM */
 196 #define CONFIG_SYS_BR2_PRELIM   (0x60000000 \
 197                                 | BR_PS_8 \
 198                                 | BR_V)
 199                                 /* 0x60000801 */
 200 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_128KB \
 201                                 | OR_GPCM_CSNT \
 202                                 | OR_GPCM_XACS \
 203                                 | OR_GPCM_SCY_3 \
 204                                 | OR_GPCM_TRLX_SET \
 205                                 | OR_GPCM_EHTR_SET \
 206                                 | OR_GPCM_EAD)
 207                                 /* 0xfffe0937 */
 208 /* local bus read write buffer mapping SRAM@0x64000000 */
 209 #define CONFIG_SYS_BR3_PRELIM   (0x62000000 \
 210                                 | BR_PS_16 \
 211                                 | BR_V)
 212                                 /* 0x62001001 */
 213
 214 #define CONFIG_SYS_OR3_PRELIM   (OR_AM_32MB \
 215                                 | OR_GPCM_CSNT \
 216                                 | OR_GPCM_XACS \
 217                                 | OR_GPCM_SCY_15 \
 218                                 | OR_GPCM_TRLX_SET \
 219                                 | OR_GPCM_EHTR_SET \
 220                                 | OR_GPCM_EAD)
 221                                 /* 0xfe0009f7 */
 222
 223 /*
 224  * Serial Port
 225  */
 226 #define CONFIG_SYS_NS16550_SERIAL
 227 #define CONFIG_SYS_NS16550_REG_SIZE     1
 228 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 229
 230 #define CONFIG_SYS_BAUDRATE_TABLE       \
 231         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 232
 233 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 234 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 235
 236 #if defined(CONFIG_PCI)
 237 /*
 238  * General PCI
 239  * Addresses are mapped 1-1.
 240  */
 241 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 242 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 243 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 244 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 245 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 246 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 247 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 248 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 249 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 250
 251 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 252 #endif
 253
 254 /*
 255  * TSEC
 256  */
 257
 258 #define CONFIG_TSEC1
 259 #ifdef CONFIG_TSEC1
 260 #define CONFIG_HAS_ETH0
 261 #define CONFIG_TSEC1_NAME       "TSEC1"
 262 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 263 #define TSEC1_PHY_ADDR          0x01
 264 #define TSEC1_FLAGS             0
 265 #define TSEC1_PHYIDX            0
 266 #endif
 267
 268 /* Options are: TSEC[0-1] */
 269 #define CONFIG_ETHPRIME                 "TSEC1"
 270
 271 /*
 272  * Environment
 273  */
 274 #define CONFIG_ENV_ADDR         \
 275                         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 276 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 277 #define CONFIG_ENV_SIZE         0x4000
 278 /* Address and size of Redundant Environment Sector */
 279 #define CONFIG_ENV_OFFSET_REDUND        \
 280                         (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
 281 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 282
 283 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 284 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 285
 286 /*
 287  * BOOTP options
 288  */
 289 #define CONFIG_BOOTP_BOOTFILESIZE
 290
 291 /*
 292  * Command line configuration.
 293  */
 294
 295 /*
 296  * Miscellaneous configurable options
 297  */
 298 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 299 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 300
 301 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
 302
 303 /*
 304  * For booting Linux, the board info and command line data
 305  * have to be in the first 256 MB of memory, since this is
 306  * the maximum mapped by the Linux kernel during initialization.
 307  */
 308                                 /* Initial Memory map for Linux*/
 309 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 310
 311 /* 0x64050000 */
 312 #define CONFIG_SYS_HRCW_LOW (\
 313         0x20000000 /* reserved, must be set */ |\
 314         HRCWL_DDRCM |\
 315         HRCWL_CSB_TO_CLKIN_4X1 | \
 316         HRCWL_CORE_TO_CSB_2_5X1)
 317
 318 /* 0xa0600004 */
 319 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
 320         HRCWH_PCI_ARBITER_ENABLE | \
 321         HRCWH_CORE_ENABLE | \
 322         HRCWH_FROM_0X00000100 | \
 323         HRCWH_BOOTSEQ_DISABLE |\
 324         HRCWH_SW_WATCHDOG_DISABLE |\
 325         HRCWH_ROM_LOC_LOCAL_16BIT | \
 326         HRCWH_TSEC1M_IN_MII | \
 327         HRCWH_BIG_ENDIAN | \
 328         HRCWH_LALE_EARLY)
 329
 330 /* System IO Config */
 331 #define CONFIG_SYS_SICRH        (0x01000000 | \
 332                                 SICRH_ETSEC2_B | \
 333                                 SICRH_ETSEC2_C | \
 334                                 SICRH_ETSEC2_D | \
 335                                 SICRH_ETSEC2_E | \
 336                                 SICRH_ETSEC2_F | \
 337                                 SICRH_ETSEC2_G | \
 338                                 SICRH_TSOBI1 | \
 339                                 SICRH_TSOBI2)
 340                                 /* 0x010fff03 */
 341 #define CONFIG_SYS_SICRL        (SICRL_LBC | \
 342                                 SICRL_SPI_A | \
 343                                 SICRL_SPI_B | \
 344                                 SICRL_SPI_C | \
 345                                 SICRL_SPI_D | \
 346                                 SICRL_ETSEC2_A)
 347                                 /* 0x33fc0003) */
 348
 349 #define CONFIG_SYS_HID0_INIT    0x000000000
 350 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 351                                  HID0_ENABLE_INSTRUCTION_CACHE)
 352
 353 #define CONFIG_SYS_HID2 HID2_HBE
 354
 355 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 356
 357 /* DDR @ 0x00000000 */
 358 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 359 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 360                                 | BATU_BL_256M \
 361                                 | BATU_VS \
 362                                 | BATU_VP)
 363
 364 #if defined(CONFIG_PCI)
 365 /* PCI @ 0x80000000 */
 366 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 367 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 368                                 | BATU_BL_256M \
 369                                 | BATU_VS \
 370                                 | BATU_VP)
 371 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 372                                 | BATL_PP_RW \
 373                                 | BATL_CACHEINHIBIT \
 374                                 | BATL_GUARDEDSTORAGE)
 375 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 376                                 | BATU_BL_256M \
 377                                 | BATU_VS \
 378                                 | BATU_VP)
 379 #else
 380 #define CONFIG_SYS_IBAT1L       (0)
 381 #define CONFIG_SYS_IBAT1U       (0)
 382 #define CONFIG_SYS_IBAT2L       (0)
 383 #define CONFIG_SYS_IBAT2U       (0)
 384 #endif
 385
 386 /* PCI2 not supported on 8313 */
 387 #define CONFIG_SYS_IBAT3L       (0)
 388 #define CONFIG_SYS_IBAT3U       (0)
 389 #define CONFIG_SYS_IBAT4L       (0)
 390 #define CONFIG_SYS_IBAT4U       (0)
 391
 392 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 393 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 394                                 | BATL_PP_RW \
 395                                 | BATL_CACHEINHIBIT \
 396                                 | BATL_GUARDEDSTORAGE)
 397 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 398                                 | BATU_BL_256M \
 399                                 | BATU_VS \
 400                                 | BATU_VP)
 401
 402 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 403 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 404 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 405
 406 /*  FPGA, SRAM, NAND @ 0x60000000 */
 407 #define CONFIG_SYS_IBAT7L       (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 408 #define CONFIG_SYS_IBAT7U       (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 409
 410 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 411 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 412 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 413 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 414 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 415 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 416 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 417 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 418 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 419 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 420 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 421 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 422 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 423 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 424 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 425 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 426
 427 #define CONFIG_NETDEV           eth0
 428
 429 #define CONFIG_HOSTNAME         "ve8313"
 430 #define CONFIG_UBOOTPATH        ve8313/u-boot.bin
 431
 432 #define CONFIG_EXTRA_ENV_SETTINGS \
 433         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
 434         "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0"                 \
 435         "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0"                    \
 436         "u-boot_addr_r=100000\0"                                        \
 437         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 438         "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE)        \
 439                 " +${filesize};"        \
 440         "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"    \
 441         "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)     \
 442         " ${filesize};"                                                 \
 443         "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
 444
 445 #endif  /* __CONFIG_H */