include/configs/ve8313.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  *
   5  * (C) Copyright 2010
   6  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   7  */
   8 /*
   9  * ve8313 board configuration file
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300             1
  19
  20 #define CONFIG_PCI_INDIRECT_BRIDGE 1
  21 #define CONFIG_FSL_ELBC         1
  22
  23 /*
  24  * On-board devices
  25  *
  26  */
  27 #define CONFIG_SYS_IMMR         0xE0000000
  28
  29 #define CONFIG_SYS_MEMTEST_START        0x00001000
  30 #define CONFIG_SYS_MEMTEST_END          0x07000000
  31
  32 #define CONFIG_SYS_ACR_PIPE_DEP         3       /* Arbiter pipeline depth */
  33 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count */
  34
  35 /*
  36  * Device configurations
  37  */
  38
  39 /*
  40  * DDR Setup
  41  */
  42 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  43 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  44 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  45
  46 /*
  47  * Manually set up DDR parameters, as this board does not
  48  * have the SPD connected to I2C.
  49  */
  50 #define CONFIG_SYS_DDR_SIZE     128     /* MB */
  51 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  52                                 | CSCONFIG_AP \
  53                                 | CSCONFIG_ODT_RD_NEVER \
  54                                 | CSCONFIG_ODT_WR_ALL \
  55                                 | CSCONFIG_ROW_BIT_13 \
  56                                 | CSCONFIG_COL_BIT_10)
  57                                 /* 0x80840102 */
  58
  59 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  60 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  61                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  62                                 | (3 << TIMING_CFG0_RRT_SHIFT) \
  63                                 | (2 << TIMING_CFG0_WWT_SHIFT) \
  64                                 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  65                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  66                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  67                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  68                                 /* 0x0e720802 */
  69 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  70                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  71                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  72                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  73                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
  74                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  75                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  76                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  77                                 /* 0x26256222 */
  78 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  79                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
  80                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  81                                 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  82                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  83                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  84                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  85                                 /* 0x029028c7 */
  86 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
  87                                 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  88                                 /* 0x03202000 */
  89 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
  90                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  91                                 | SDRAM_CFG_DBW_32)
  92                                 /* 0x43080000 */
  93 #define CONFIG_SYS_SDRAM_CFG2   0x00401000
  94 #define CONFIG_SYS_DDR_MODE     ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
  95                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  96                                 /* 0x44400232 */
  97 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
  98
  99 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 100                                 /*0x02000000*/
 101 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 102                                 | DDRCDR_PZ_NOMZ \
 103                                 | DDRCDR_NZ_NOMZ \
 104                                 | DDRCDR_M_ODR)
 105                                 /* 0x73000002 */
 106
 107 /*
 108  * FLASH on the Local Bus
 109  */
 110 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 111 #define CONFIG_SYS_FLASH_SIZE           32      /* size in MB */
 112 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 113
 114 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 115 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per dev */
 116
 117 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 118 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 119
 120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 121
 122 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 123 #define CONFIG_SYS_RAMBOOT
 124 #endif
 125
 126 #define CONFIG_SYS_INIT_RAM_LOCK        1
 127 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
 128 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 129
 130 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 131                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 132 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 133
 134 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 135 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)
 136 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 137
 138 /*
 139  * Local Bus LCRR and LBCR regs
 140  */
 141 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_3
 142 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_2
 143
 144 #define CONFIG_SYS_LBC_LBCR     0x00040000
 145
 146 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 147
 148 /*
 149  * NAND settings
 150  */
 151 #define CONFIG_SYS_NAND_BASE            0x61000000
 152 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 153 #define CONFIG_NAND_FSL_ELBC 1
 154 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 155
 156
 157
 158 /* Still needed for spl_minimal.c */
 159 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 160 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 161
 162
 163
 164 /*
 165  * Serial Port
 166  */
 167 #define CONFIG_SYS_NS16550_SERIAL
 168 #define CONFIG_SYS_NS16550_REG_SIZE     1
 169 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 170
 171 #define CONFIG_SYS_BAUDRATE_TABLE       \
 172         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 173
 174 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 175 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 176
 177 #if defined(CONFIG_PCI)
 178 /*
 179  * General PCI
 180  * Addresses are mapped 1-1.
 181  */
 182 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 183 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 184 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 185 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 186 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 187 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 188 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 189 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 190 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 191
 192 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 193 #endif
 194
 195 /*
 196  * TSEC
 197  */
 198
 199 #define CONFIG_TSEC1
 200 #ifdef CONFIG_TSEC1
 201 #define CONFIG_HAS_ETH0
 202 #define CONFIG_TSEC1_NAME       "TSEC1"
 203 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 204 #define TSEC1_PHY_ADDR          0x01
 205 #define TSEC1_FLAGS             0
 206 #define TSEC1_PHYIDX            0
 207 #endif
 208
 209 /* Options are: TSEC[0-1] */
 210 #define CONFIG_ETHPRIME                 "TSEC1"
 211
 212 /*
 213  * Environment
 214  */
 215 #define CONFIG_ENV_ADDR         \
 216                         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 217 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 218 #define CONFIG_ENV_SIZE         0x4000
 219 /* Address and size of Redundant Environment Sector */
 220 #define CONFIG_ENV_OFFSET_REDUND        \
 221                         (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
 222 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 223
 224 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 225 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 226
 227 /*
 228  * BOOTP options
 229  */
 230 #define CONFIG_BOOTP_BOOTFILESIZE
 231
 232 /*
 233  * Command line configuration.
 234  */
 235
 236 /*
 237  * Miscellaneous configurable options
 238  */
 239 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 240 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 241
 242 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
 243
 244 /*
 245  * For booting Linux, the board info and command line data
 246  * have to be in the first 256 MB of memory, since this is
 247  * the maximum mapped by the Linux kernel during initialization.
 248  */
 249                                 /* Initial Memory map for Linux*/
 250 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 251
 252 /* System IO Config */
 253 #define CONFIG_SYS_SICRH        (0x01000000 | \
 254                                 SICRH_ETSEC2_B | \
 255                                 SICRH_ETSEC2_C | \
 256                                 SICRH_ETSEC2_D | \
 257                                 SICRH_ETSEC2_E | \
 258                                 SICRH_ETSEC2_F | \
 259                                 SICRH_ETSEC2_G | \
 260                                 SICRH_TSOBI1 | \
 261                                 SICRH_TSOBI2)
 262                                 /* 0x010fff03 */
 263 #define CONFIG_SYS_SICRL        (SICRL_LBC | \
 264                                 SICRL_SPI_A | \
 265                                 SICRL_SPI_B | \
 266                                 SICRL_SPI_C | \
 267                                 SICRL_SPI_D | \
 268                                 SICRL_ETSEC2_A)
 269                                 /* 0x33fc0003) */
 270
 271 #define CONFIG_NETDEV           eth0
 272
 273 #define CONFIG_HOSTNAME         "ve8313"
 274 #define CONFIG_UBOOTPATH        ve8313/u-boot.bin
 275
 276 #define CONFIG_EXTRA_ENV_SETTINGS \
 277         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
 278         "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0"                 \
 279         "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0"                    \
 280         "u-boot_addr_r=100000\0"                                        \
 281         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 282         "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE)        \
 283                 " +${filesize};"        \
 284         "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"    \
 285         "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)     \
 286         " ${filesize};"                                                 \
 287         "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
 288
 289 #endif  /* __CONFIG_H */