1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
6 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
9 * ve8313 board configuration file
16 * High Level Configuration Options
20 #define CONFIG_PCI_INDIRECT_BRIDGE 1
21 #define CONFIG_FSL_ELBC 1
27 #define CONFIG_SYS_IMMR 0xE0000000
29 #define CONFIG_SYS_MEMTEST_START 0x00001000
30 #define CONFIG_SYS_MEMTEST_END 0x07000000
32 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
33 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
36 * Device configurations
42 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
43 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
44 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
47 * Manually set up DDR parameters, as this board does not
48 * have the SPD connected to I2C.
50 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
51 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
53 | CSCONFIG_ODT_RD_NEVER \
54 | CSCONFIG_ODT_WR_ALL \
55 | CSCONFIG_ROW_BIT_13 \
56 | CSCONFIG_COL_BIT_10)
59 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
60 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
61 | (0 << TIMING_CFG0_WRT_SHIFT) \
62 | (3 << TIMING_CFG0_RRT_SHIFT) \
63 | (2 << TIMING_CFG0_WWT_SHIFT) \
64 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
65 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
66 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
67 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
69 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
70 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
71 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
72 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
73 | (6 << TIMING_CFG1_REFREC_SHIFT) \
74 | (2 << TIMING_CFG1_WRREC_SHIFT) \
75 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
76 | (2 << TIMING_CFG1_WRTORD_SHIFT))
78 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
79 | (5 << TIMING_CFG2_CPO_SHIFT) \
80 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
81 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
82 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
83 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
84 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
86 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
87 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
89 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
90 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
93 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
94 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
95 | (0x0232 << SDRAM_MODE_SD_SHIFT))
97 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
99 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
101 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
108 * FLASH on the Local Bus
110 #define CONFIG_SYS_FLASH_BASE 0xFE000000
111 #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
112 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
114 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
115 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
117 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
118 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
120 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
121 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
123 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
125 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
126 #define CONFIG_SYS_RAMBOOT
129 #define CONFIG_SYS_INIT_RAM_LOCK 1
130 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
131 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
133 #define CONFIG_SYS_GBL_DATA_OFFSET \
134 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
135 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
137 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
138 #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
139 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
142 * Local Bus LCRR and LBCR regs
144 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
145 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
147 #define CONFIG_SYS_LBC_LBCR 0x00040000
149 #define CONFIG_SYS_LBC_MRTPR 0x20000000
154 #define CONFIG_SYS_NAND_BASE 0x61000000
155 #define CONFIG_SYS_MAX_NAND_DEVICE 1
156 #define CONFIG_NAND_FSL_ELBC 1
157 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
160 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
161 | BR_PS_16 /* 16 bit */ \
162 | BR_MS_GPCM /* MSEL = GPCM */ \
164 #define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \
172 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
178 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
183 | OR_FCM_TRLX) /* 0xffff90ac */
185 /* Still needed for spl_minimal.c */
186 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
187 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
189 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
190 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
192 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
193 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
196 #define CONFIG_SYS_BR2_PRELIM (0x60000000 \
200 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
208 /* local bus read write buffer mapping SRAM@0x64000000 */
209 #define CONFIG_SYS_BR3_PRELIM (0x62000000 \
214 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \
226 #define CONFIG_SYS_NS16550_SERIAL
227 #define CONFIG_SYS_NS16550_REG_SIZE 1
228 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
230 #define CONFIG_SYS_BAUDRATE_TABLE \
231 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
233 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
234 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
236 #if defined(CONFIG_PCI)
239 * Addresses are mapped 1-1.
241 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
242 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
243 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
244 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
245 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
246 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
247 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
248 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
249 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
251 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
260 #define CONFIG_HAS_ETH0
261 #define CONFIG_TSEC1_NAME "TSEC1"
262 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
263 #define TSEC1_PHY_ADDR 0x01
264 #define TSEC1_FLAGS 0
265 #define TSEC1_PHYIDX 0
268 /* Options are: TSEC[0-1] */
269 #define CONFIG_ETHPRIME "TSEC1"
274 #define CONFIG_ENV_ADDR \
275 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
276 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
277 #define CONFIG_ENV_SIZE 0x4000
278 /* Address and size of Redundant Environment Sector */
279 #define CONFIG_ENV_OFFSET_REDUND \
280 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
281 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
283 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
284 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
289 #define CONFIG_BOOTP_BOOTFILESIZE
292 * Command line configuration.
296 * Miscellaneous configurable options
298 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
299 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
301 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
304 * For booting Linux, the board info and command line data
305 * have to be in the first 256 MB of memory, since this is
306 * the maximum mapped by the Linux kernel during initialization.
308 /* Initial Memory map for Linux*/
309 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
311 /* System IO Config */
312 #define CONFIG_SYS_SICRH (0x01000000 | \
322 #define CONFIG_SYS_SICRL (SICRL_LBC | \
330 #define CONFIG_SYS_HID0_INIT 0x000000000
331 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
332 HID0_ENABLE_INSTRUCTION_CACHE)
334 #define CONFIG_SYS_HID2 HID2_HBE
336 /* DDR @ 0x00000000 */
337 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
338 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
343 #if defined(CONFIG_PCI)
344 /* PCI @ 0x80000000 */
345 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
346 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
350 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
352 | BATL_CACHEINHIBIT \
353 | BATL_GUARDEDSTORAGE)
354 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
359 #define CONFIG_SYS_IBAT1L (0)
360 #define CONFIG_SYS_IBAT1U (0)
361 #define CONFIG_SYS_IBAT2L (0)
362 #define CONFIG_SYS_IBAT2U (0)
365 /* PCI2 not supported on 8313 */
366 #define CONFIG_SYS_IBAT3L (0)
367 #define CONFIG_SYS_IBAT3U (0)
368 #define CONFIG_SYS_IBAT4L (0)
369 #define CONFIG_SYS_IBAT4U (0)
371 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
372 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
374 | BATL_CACHEINHIBIT \
375 | BATL_GUARDEDSTORAGE)
376 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
381 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
382 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
383 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
385 /* FPGA, SRAM, NAND @ 0x60000000 */
386 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
387 #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
389 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
390 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
391 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
392 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
393 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
394 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
395 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
396 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
397 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
398 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
399 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
400 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
401 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
402 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
403 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
404 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
406 #define CONFIG_NETDEV eth0
408 #define CONFIG_HOSTNAME "ve8313"
409 #define CONFIG_UBOOTPATH ve8313/u-boot.bin
411 #define CONFIG_EXTRA_ENV_SETTINGS \
412 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
413 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
414 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
415 "u-boot_addr_r=100000\0" \
416 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
417 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
419 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
420 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
422 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
424 #endif /* __CONFIG_H */