include/configs/ve8313.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  *
   5  * (C) Copyright 2010
   6  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   7  */
   8 /*
   9  * ve8313 board configuration file
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300             1
  19
  20 #define CONFIG_PCI_INDIRECT_BRIDGE 1
  21 #define CONFIG_FSL_ELBC         1
  22
  23 /*
  24  * On-board devices
  25  *
  26  */
  27 #define CONFIG_SYS_MEMTEST_START        0x00001000
  28 #define CONFIG_SYS_MEMTEST_END          0x07000000
  29
  30 /*
  31  * Device configurations
  32  */
  33
  34 /*
  35  * DDR Setup
  36  */
  37 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory*/
  38 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_SDRAM_BASE
  39
  40 /*
  41  * Manually set up DDR parameters, as this board does not
  42  * have the SPD connected to I2C.
  43  */
  44 #define CONFIG_SYS_DDR_SIZE     128     /* MB */
  45 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  46                                 | CSCONFIG_AP \
  47                                 | CSCONFIG_ODT_RD_NEVER \
  48                                 | CSCONFIG_ODT_WR_ALL \
  49                                 | CSCONFIG_ROW_BIT_13 \
  50                                 | CSCONFIG_COL_BIT_10)
  51                                 /* 0x80840102 */
  52
  53 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  54 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  55                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  56                                 | (3 << TIMING_CFG0_RRT_SHIFT) \
  57                                 | (2 << TIMING_CFG0_WWT_SHIFT) \
  58                                 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  59                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  60                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  61                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  62                                 /* 0x0e720802 */
  63 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  64                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  65                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  66                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  67                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
  68                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  69                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  70                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  71                                 /* 0x26256222 */
  72 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  73                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
  74                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  75                                 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  76                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  77                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  78                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  79                                 /* 0x029028c7 */
  80 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
  81                                 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  82                                 /* 0x03202000 */
  83 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
  84                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  85                                 | SDRAM_CFG_DBW_32)
  86                                 /* 0x43080000 */
  87 #define CONFIG_SYS_SDRAM_CFG2   0x00401000
  88 #define CONFIG_SYS_DDR_MODE     ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
  89                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  90                                 /* 0x44400232 */
  91 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
  92
  93 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  94                                 /*0x02000000*/
  95 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  96                                 | DDRCDR_PZ_NOMZ \
  97                                 | DDRCDR_NZ_NOMZ \
  98                                 | DDRCDR_M_ODR)
  99                                 /* 0x73000002 */
 100
 101 /*
 102  * FLASH on the Local Bus
 103  */
 104 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 105 #define CONFIG_SYS_FLASH_SIZE           32      /* size in MB */
 106 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 107
 108 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 109 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per dev */
 110
 111 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 112 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 113
 114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 115
 116 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 117 #define CONFIG_SYS_RAMBOOT
 118 #endif
 119
 120 #define CONFIG_SYS_INIT_RAM_LOCK        1
 121 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
 122 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 123
 124 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 125                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 126 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 127
 128 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 129 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)
 130 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 131
 132 /*
 133  * Local Bus LCRR and LBCR regs
 134  */
 135 #define CONFIG_SYS_LBC_LBCR     0x00040000
 136
 137 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 138
 139 /*
 140  * NAND settings
 141  */
 142 #define CONFIG_SYS_NAND_BASE            0x61000000
 143 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 144 #define CONFIG_NAND_FSL_ELBC 1
 145 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 146
 147
 148
 149 /* Still needed for spl_minimal.c */
 150 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 151 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 152
 153
 154
 155 /*
 156  * Serial Port
 157  */
 158 #define CONFIG_SYS_NS16550_SERIAL
 159 #define CONFIG_SYS_NS16550_REG_SIZE     1
 160 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 161
 162 #define CONFIG_SYS_BAUDRATE_TABLE       \
 163         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 164
 165 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 166 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 167
 168 #if defined(CONFIG_PCI)
 169 /*
 170  * General PCI
 171  * Addresses are mapped 1-1.
 172  */
 173 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 174 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 175 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 176 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 177 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 178 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 179 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 180 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 181 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 182
 183 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 184 #endif
 185
 186 /*
 187  * TSEC
 188  */
 189
 190 #define CONFIG_TSEC1
 191 #ifdef CONFIG_TSEC1
 192 #define CONFIG_HAS_ETH0
 193 #define CONFIG_TSEC1_NAME       "TSEC1"
 194 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 195 #define TSEC1_PHY_ADDR          0x01
 196 #define TSEC1_FLAGS             0
 197 #define TSEC1_PHYIDX            0
 198 #endif
 199
 200 /* Options are: TSEC[0-1] */
 201 #define CONFIG_ETHPRIME                 "TSEC1"
 202
 203 /*
 204  * Environment
 205  */
 206 #define CONFIG_ENV_ADDR         \
 207                         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 208 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 209 #define CONFIG_ENV_SIZE         0x4000
 210 /* Address and size of Redundant Environment Sector */
 211 #define CONFIG_ENV_OFFSET_REDUND        \
 212                         (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
 213 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 214
 215 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 216 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 217
 218 /*
 219  * BOOTP options
 220  */
 221 #define CONFIG_BOOTP_BOOTFILESIZE
 222
 223 /*
 224  * Command line configuration.
 225  */
 226
 227 /*
 228  * Miscellaneous configurable options
 229  */
 230 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 231 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 232
 233 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
 234
 235 /*
 236  * For booting Linux, the board info and command line data
 237  * have to be in the first 256 MB of memory, since this is
 238  * the maximum mapped by the Linux kernel during initialization.
 239  */
 240                                 /* Initial Memory map for Linux*/
 241 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 242
 243 /* System IO Config */
 244 #define CONFIG_SYS_SICRH        (0x01000000 | \
 245                                 SICRH_ETSEC2_B | \
 246                                 SICRH_ETSEC2_C | \
 247                                 SICRH_ETSEC2_D | \
 248                                 SICRH_ETSEC2_E | \
 249                                 SICRH_ETSEC2_F | \
 250                                 SICRH_ETSEC2_G | \
 251                                 SICRH_TSOBI1 | \
 252                                 SICRH_TSOBI2)
 253                                 /* 0x010fff03 */
 254 #define CONFIG_SYS_SICRL        (SICRL_LBC | \
 255                                 SICRL_SPI_A | \
 256                                 SICRL_SPI_B | \
 257                                 SICRL_SPI_C | \
 258                                 SICRL_SPI_D | \
 259                                 SICRL_ETSEC2_A)
 260                                 /* 0x33fc0003) */
 261
 262 #define CONFIG_NETDEV           eth0
 263
 264 #define CONFIG_HOSTNAME         "ve8313"
 265 #define CONFIG_UBOOTPATH        ve8313/u-boot.bin
 266
 267 #define CONFIG_EXTRA_ENV_SETTINGS \
 268         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
 269         "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0"                 \
 270         "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0"                    \
 271         "u-boot_addr_r=100000\0"                                        \
 272         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 273         "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE)        \
 274                 " +${filesize};"        \
 275         "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"    \
 276         "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)     \
 277         " ${filesize};"                                                 \
 278         "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
 279
 280 #endif  /* __CONFIG_H */