include/configs/ve8313.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   3  *
   4  * (C) Copyright 2010
   5  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 /*
  10  * ve8313 board configuration file
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_E300             1
  20 #define CONFIG_MPC831x          1
  21 #define CONFIG_MPC8313          1
  22
  23 #define CONFIG_PCI_INDIRECT_BRIDGE 1
  24 #define CONFIG_FSL_ELBC         1
  25
  26 /*
  27  * On-board devices
  28  *
  29  */
  30 #define CONFIG_83XX_CLKIN       32000000        /* in Hz */
  31
  32 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  33
  34 #define CONFIG_SYS_IMMR         0xE0000000
  35
  36 #define CONFIG_SYS_MEMTEST_START        0x00001000
  37 #define CONFIG_SYS_MEMTEST_END          0x07000000
  38
  39 #define CONFIG_SYS_ACR_PIPE_DEP         3       /* Arbiter pipeline depth */
  40 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count */
  41
  42 /*
  43  * Device configurations
  44  */
  45
  46 /*
  47  * DDR Setup
  48  */
  49 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  50 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  51 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  52
  53 /*
  54  * Manually set up DDR parameters, as this board does not
  55  * have the SPD connected to I2C.
  56  */
  57 #define CONFIG_SYS_DDR_SIZE     128     /* MB */
  58 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  59                                 | CSCONFIG_AP \
  60                                 | CSCONFIG_ODT_RD_NEVER \
  61                                 | CSCONFIG_ODT_WR_ALL \
  62                                 | CSCONFIG_ROW_BIT_13 \
  63                                 | CSCONFIG_COL_BIT_10)
  64                                 /* 0x80840102 */
  65
  66 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  67 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  68                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  69                                 | (3 << TIMING_CFG0_RRT_SHIFT) \
  70                                 | (2 << TIMING_CFG0_WWT_SHIFT) \
  71                                 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  72                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  73                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  74                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  75                                 /* 0x0e720802 */
  76 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  77                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  78                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  79                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  80                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
  81                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  82                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  83                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  84                                 /* 0x26256222 */
  85 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  86                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
  87                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  88                                 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  89                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  90                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  91                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  92                                 /* 0x029028c7 */
  93 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
  94                                 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  95                                 /* 0x03202000 */
  96 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
  97                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  98                                 | SDRAM_CFG_DBW_32)
  99                                 /* 0x43080000 */
 100 #define CONFIG_SYS_SDRAM_CFG2   0x00401000
 101 #define CONFIG_SYS_DDR_MODE     ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
 102                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 103                                 /* 0x44400232 */
 104 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 105
 106 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 107                                 /*0x02000000*/
 108 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 109                                 | DDRCDR_PZ_NOMZ \
 110                                 | DDRCDR_NZ_NOMZ \
 111                                 | DDRCDR_M_ODR)
 112                                 /* 0x73000002 */
 113
 114 /*
 115  * FLASH on the Local Bus
 116  */
 117 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 118 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 119 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 120 #define CONFIG_SYS_FLASH_SIZE           32      /* size in MB */
 121 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 122 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
 123
 124 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
 125                                         | BR_PS_16      /* 16 bit */ \
 126                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 127                                         | BR_V)         /* valid */
 128 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 129                                         | OR_GPCM_CSNT \
 130                                         | OR_GPCM_ACS_DIV4 \
 131                                         | OR_GPCM_SCY_5 \
 132                                         | OR_GPCM_TRLX_SET \
 133                                         | OR_GPCM_EAD)
 134                                         /* 0xfe000c55 */
 135
 136 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 137 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 138
 139 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 140 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per dev */
 141
 142 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 143 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 144
 145 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 146
 147 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 148 #define CONFIG_SYS_RAMBOOT
 149 #endif
 150
 151 #define CONFIG_SYS_INIT_RAM_LOCK        1
 152 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
 153 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 154
 155 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 156                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 157 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 158
 159 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 160 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)
 161 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 162
 163 /*
 164  * Local Bus LCRR and LBCR regs
 165  */
 166 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_3
 167 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_2
 168
 169 #define CONFIG_SYS_LBC_LBCR     0x00040000
 170
 171 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 172
 173 /*
 174  * NAND settings
 175  */
 176 #define CONFIG_SYS_NAND_BASE            0x61000000
 177 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 178 #define CONFIG_NAND_FSL_ELBC 1
 179 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 180
 181 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 182                                         | BR_PS_8               \
 183                                         | BR_DECC_CHK_GEN       \
 184                                         | BR_MS_FCM             \
 185                                         | BR_V) /* valid */
 186                                         /* 0x61000c21 */
 187 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB \
 188                                         | OR_FCM_BCTLD \
 189                                         | OR_FCM_CHT \
 190                                         | OR_FCM_SCY_2 \
 191                                         | OR_FCM_RST \
 192                                         | OR_FCM_TRLX)
 193                                         /* 0xffff90ac */
 194
 195 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 196 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 197 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 198 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 199
 200 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 201 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 202
 203 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 204 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 205
 206 /* CS2 NvRAM */
 207 #define CONFIG_SYS_BR2_PRELIM   (0x60000000 \
 208                                 | BR_PS_8 \
 209                                 | BR_V)
 210                                 /* 0x60000801 */
 211 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_128KB \
 212                                 | OR_GPCM_CSNT \
 213                                 | OR_GPCM_XACS \
 214                                 | OR_GPCM_SCY_3 \
 215                                 | OR_GPCM_TRLX_SET \
 216                                 | OR_GPCM_EHTR_SET \
 217                                 | OR_GPCM_EAD)
 218                                 /* 0xfffe0937 */
 219 /* local bus read write buffer mapping SRAM@0x64000000 */
 220 #define CONFIG_SYS_BR3_PRELIM   (0x62000000 \
 221                                 | BR_PS_16 \
 222                                 | BR_V)
 223                                 /* 0x62001001 */
 224
 225 #define CONFIG_SYS_OR3_PRELIM   (OR_AM_32MB \
 226                                 | OR_GPCM_CSNT \
 227                                 | OR_GPCM_XACS \
 228                                 | OR_GPCM_SCY_15 \
 229                                 | OR_GPCM_TRLX_SET \
 230                                 | OR_GPCM_EHTR_SET \
 231                                 | OR_GPCM_EAD)
 232                                 /* 0xfe0009f7 */
 233
 234 /*
 235  * Serial Port
 236  */
 237 #define CONFIG_SYS_NS16550_SERIAL
 238 #define CONFIG_SYS_NS16550_REG_SIZE     1
 239 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 240
 241 #define CONFIG_SYS_BAUDRATE_TABLE       \
 242         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 243
 244 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 245 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 246
 247 #if defined(CONFIG_PCI)
 248 /*
 249  * General PCI
 250  * Addresses are mapped 1-1.
 251  */
 252 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 253 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 254 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 255 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 256 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 257 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 258 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 259 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 260 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 261
 262 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 263 #endif
 264
 265 /*
 266  * TSEC
 267  */
 268
 269 #define CONFIG_TSEC1
 270 #ifdef CONFIG_TSEC1
 271 #define CONFIG_HAS_ETH0
 272 #define CONFIG_TSEC1_NAME       "TSEC1"
 273 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 274 #define TSEC1_PHY_ADDR          0x01
 275 #define TSEC1_FLAGS             0
 276 #define TSEC1_PHYIDX            0
 277 #endif
 278
 279 /* Options are: TSEC[0-1] */
 280 #define CONFIG_ETHPRIME                 "TSEC1"
 281
 282 /*
 283  * Environment
 284  */
 285 #define CONFIG_ENV_ADDR         \
 286                         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 287 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 288 #define CONFIG_ENV_SIZE         0x4000
 289 /* Address and size of Redundant Environment Sector */
 290 #define CONFIG_ENV_OFFSET_REDUND        \
 291                         (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
 292 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 293
 294 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 295 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 296
 297 /*
 298  * BOOTP options
 299  */
 300 #define CONFIG_BOOTP_BOOTFILESIZE
 301
 302 /*
 303  * Command line configuration.
 304  */
 305
 306 /*
 307  * Miscellaneous configurable options
 308  */
 309 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 310 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 311
 312 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
 313
 314 /*
 315  * For booting Linux, the board info and command line data
 316  * have to be in the first 256 MB of memory, since this is
 317  * the maximum mapped by the Linux kernel during initialization.
 318  */
 319                                 /* Initial Memory map for Linux*/
 320 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 321
 322 /* 0x64050000 */
 323 #define CONFIG_SYS_HRCW_LOW (\
 324         0x20000000 /* reserved, must be set */ |\
 325         HRCWL_DDRCM |\
 326         HRCWL_CSB_TO_CLKIN_4X1 | \
 327         HRCWL_CORE_TO_CSB_2_5X1)
 328
 329 /* 0xa0600004 */
 330 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
 331         HRCWH_PCI_ARBITER_ENABLE | \
 332         HRCWH_CORE_ENABLE | \
 333         HRCWH_FROM_0X00000100 | \
 334         HRCWH_BOOTSEQ_DISABLE |\
 335         HRCWH_SW_WATCHDOG_DISABLE |\
 336         HRCWH_ROM_LOC_LOCAL_16BIT | \
 337         HRCWH_TSEC1M_IN_MII | \
 338         HRCWH_BIG_ENDIAN | \
 339         HRCWH_LALE_EARLY)
 340
 341 /* System IO Config */
 342 #define CONFIG_SYS_SICRH        (0x01000000 | \
 343                                 SICRH_ETSEC2_B | \
 344                                 SICRH_ETSEC2_C | \
 345                                 SICRH_ETSEC2_D | \
 346                                 SICRH_ETSEC2_E | \
 347                                 SICRH_ETSEC2_F | \
 348                                 SICRH_ETSEC2_G | \
 349                                 SICRH_TSOBI1 | \
 350                                 SICRH_TSOBI2)
 351                                 /* 0x010fff03 */
 352 #define CONFIG_SYS_SICRL        (SICRL_LBC | \
 353                                 SICRL_SPI_A | \
 354                                 SICRL_SPI_B | \
 355                                 SICRL_SPI_C | \
 356                                 SICRL_SPI_D | \
 357                                 SICRL_ETSEC2_A)
 358                                 /* 0x33fc0003) */
 359
 360 #define CONFIG_SYS_HID0_INIT    0x000000000
 361 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 362                                  HID0_ENABLE_INSTRUCTION_CACHE)
 363
 364 #define CONFIG_SYS_HID2 HID2_HBE
 365
 366 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 367
 368 /* DDR @ 0x00000000 */
 369 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 370 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 371                                 | BATU_BL_256M \
 372                                 | BATU_VS \
 373                                 | BATU_VP)
 374
 375 #if defined(CONFIG_PCI)
 376 /* PCI @ 0x80000000 */
 377 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 378 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 379                                 | BATU_BL_256M \
 380                                 | BATU_VS \
 381                                 | BATU_VP)
 382 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 383                                 | BATL_PP_RW \
 384                                 | BATL_CACHEINHIBIT \
 385                                 | BATL_GUARDEDSTORAGE)
 386 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 387                                 | BATU_BL_256M \
 388                                 | BATU_VS \
 389                                 | BATU_VP)
 390 #else
 391 #define CONFIG_SYS_IBAT1L       (0)
 392 #define CONFIG_SYS_IBAT1U       (0)
 393 #define CONFIG_SYS_IBAT2L       (0)
 394 #define CONFIG_SYS_IBAT2U       (0)
 395 #endif
 396
 397 /* PCI2 not supported on 8313 */
 398 #define CONFIG_SYS_IBAT3L       (0)
 399 #define CONFIG_SYS_IBAT3U       (0)
 400 #define CONFIG_SYS_IBAT4L       (0)
 401 #define CONFIG_SYS_IBAT4U       (0)
 402
 403 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 404 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 405                                 | BATL_PP_RW \
 406                                 | BATL_CACHEINHIBIT \
 407                                 | BATL_GUARDEDSTORAGE)
 408 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 409                                 | BATU_BL_256M \
 410                                 | BATU_VS \
 411                                 | BATU_VP)
 412
 413 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 414 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 415 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 416
 417 /*  FPGA, SRAM, NAND @ 0x60000000 */
 418 #define CONFIG_SYS_IBAT7L       (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 419 #define CONFIG_SYS_IBAT7U       (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 420
 421 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 422 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 423 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 424 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 425 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 426 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 427 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 428 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 429 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 430 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 431 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 432 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 433 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 434 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 435 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 436 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 437
 438 #define CONFIG_NETDEV           eth0
 439
 440 #define CONFIG_HOSTNAME         "ve8313"
 441 #define CONFIG_UBOOTPATH        ve8313/u-boot.bin
 442
 443 #define CONFIG_EXTRA_ENV_SETTINGS \
 444         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
 445         "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0"                 \
 446         "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0"                    \
 447         "u-boot_addr_r=100000\0"                                        \
 448         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 449         "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE)        \
 450                 " +${filesize};"        \
 451         "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"    \
 452         "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)     \
 453         " ${filesize};"                                                 \
 454         "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
 455
 456 #endif  /* __CONFIG_H */