1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
6 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
9 * ve8313 board configuration file
16 * High Level Configuration Options
20 #define CONFIG_PCI_INDIRECT_BRIDGE 1
21 #define CONFIG_FSL_ELBC 1
27 #define CONFIG_SYS_MEMTEST_START 0x00001000
28 #define CONFIG_SYS_MEMTEST_END 0x07000000
31 * Device configurations
37 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
38 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
39 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
42 * Manually set up DDR parameters, as this board does not
43 * have the SPD connected to I2C.
45 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
46 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
48 | CSCONFIG_ODT_RD_NEVER \
49 | CSCONFIG_ODT_WR_ALL \
50 | CSCONFIG_ROW_BIT_13 \
51 | CSCONFIG_COL_BIT_10)
54 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
55 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
56 | (0 << TIMING_CFG0_WRT_SHIFT) \
57 | (3 << TIMING_CFG0_RRT_SHIFT) \
58 | (2 << TIMING_CFG0_WWT_SHIFT) \
59 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
60 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
61 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
62 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
64 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
65 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
66 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
67 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
68 | (6 << TIMING_CFG1_REFREC_SHIFT) \
69 | (2 << TIMING_CFG1_WRREC_SHIFT) \
70 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
71 | (2 << TIMING_CFG1_WRTORD_SHIFT))
73 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
74 | (5 << TIMING_CFG2_CPO_SHIFT) \
75 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
76 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
77 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
78 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
79 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
81 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
82 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
84 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
85 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
88 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
89 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
90 | (0x0232 << SDRAM_MODE_SD_SHIFT))
92 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
94 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
96 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
103 * FLASH on the Local Bus
105 #define CONFIG_SYS_FLASH_BASE 0xFE000000
106 #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
107 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
109 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
110 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
112 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
113 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
117 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
118 #define CONFIG_SYS_RAMBOOT
121 #define CONFIG_SYS_INIT_RAM_LOCK 1
122 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
123 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
125 #define CONFIG_SYS_GBL_DATA_OFFSET \
126 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
127 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
129 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
130 #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
131 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
134 * Local Bus LCRR and LBCR regs
136 #define CONFIG_SYS_LBC_LBCR 0x00040000
138 #define CONFIG_SYS_LBC_MRTPR 0x20000000
143 #define CONFIG_SYS_NAND_BASE 0x61000000
144 #define CONFIG_SYS_MAX_NAND_DEVICE 1
145 #define CONFIG_NAND_FSL_ELBC 1
146 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
150 /* Still needed for spl_minimal.c */
151 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
152 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
159 #define CONFIG_SYS_NS16550_SERIAL
160 #define CONFIG_SYS_NS16550_REG_SIZE 1
161 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
163 #define CONFIG_SYS_BAUDRATE_TABLE \
164 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
166 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
167 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
169 #if defined(CONFIG_PCI)
172 * Addresses are mapped 1-1.
174 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
175 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
176 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
177 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
178 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
179 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
180 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
181 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
182 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
184 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
193 #define CONFIG_HAS_ETH0
194 #define CONFIG_TSEC1_NAME "TSEC1"
195 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
196 #define TSEC1_PHY_ADDR 0x01
197 #define TSEC1_FLAGS 0
198 #define TSEC1_PHYIDX 0
201 /* Options are: TSEC[0-1] */
202 #define CONFIG_ETHPRIME "TSEC1"
207 #define CONFIG_ENV_ADDR \
208 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
209 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
210 #define CONFIG_ENV_SIZE 0x4000
211 /* Address and size of Redundant Environment Sector */
212 #define CONFIG_ENV_OFFSET_REDUND \
213 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
214 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
216 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
217 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
222 #define CONFIG_BOOTP_BOOTFILESIZE
225 * Command line configuration.
229 * Miscellaneous configurable options
231 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
232 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
234 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
237 * For booting Linux, the board info and command line data
238 * have to be in the first 256 MB of memory, since this is
239 * the maximum mapped by the Linux kernel during initialization.
241 /* Initial Memory map for Linux*/
242 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
244 /* System IO Config */
245 #define CONFIG_SYS_SICRH (0x01000000 | \
255 #define CONFIG_SYS_SICRL (SICRL_LBC | \
263 #define CONFIG_NETDEV eth0
265 #define CONFIG_HOSTNAME "ve8313"
266 #define CONFIG_UBOOTPATH ve8313/u-boot.bin
268 #define CONFIG_EXTRA_ENV_SETTINGS \
269 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
270 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
271 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
272 "u-boot_addr_r=100000\0" \
273 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
274 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
276 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
277 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
279 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
281 #endif /* __CONFIG_H */