Merge branch 'master' of git://git.denx.de/u-boot-usb
[platform/kernel/u-boot.git] / include / configs / ve8313.h
1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
3  *
4  * (C) Copyright 2010
5  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9 /*
10  * ve8313 board configuration file
11  */
12
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15
16 /*
17  * High Level Configuration Options
18  */
19 #define CONFIG_E300             1
20 #define CONFIG_MPC831x          1
21 #define CONFIG_MPC8313          1
22 #define CONFIG_VE8313           1
23
24 #ifndef CONFIG_SYS_TEXT_BASE
25 #define CONFIG_SYS_TEXT_BASE    0xfe000000
26 #endif
27
28 #define CONFIG_PCI_INDIRECT_BRIDGE 1
29 #define CONFIG_FSL_ELBC         1
30
31 #define CONFIG_BOARD_EARLY_INIT_F       1
32
33 /*
34  * On-board devices
35  *
36  */
37 #define CONFIG_83XX_CLKIN       32000000        /* in Hz */
38
39 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
40
41 #define CONFIG_SYS_IMMR         0xE0000000
42
43 #define CONFIG_SYS_MEMTEST_START        0x00001000
44 #define CONFIG_SYS_MEMTEST_END          0x07000000
45
46 #define CONFIG_SYS_ACR_PIPE_DEP         3       /* Arbiter pipeline depth */
47 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count */
48
49 /*
50  * Device configurations
51  */
52
53 /*
54  * DDR Setup
55  */
56 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
57 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
58 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
59
60 /*
61  * Manually set up DDR parameters, as this board does not
62  * have the SPD connected to I2C.
63  */
64 #define CONFIG_SYS_DDR_SIZE     128     /* MB */
65 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
66                                 | CSCONFIG_AP \
67                                 | CSCONFIG_ODT_RD_NEVER \
68                                 | CSCONFIG_ODT_WR_ALL \
69                                 | CSCONFIG_ROW_BIT_13 \
70                                 | CSCONFIG_COL_BIT_10)
71                                 /* 0x80840102 */
72
73 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
74 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
75                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
76                                 | (3 << TIMING_CFG0_RRT_SHIFT) \
77                                 | (2 << TIMING_CFG0_WWT_SHIFT) \
78                                 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
79                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
80                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
81                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
82                                 /* 0x0e720802 */
83 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
84                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
85                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
86                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
87                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
88                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
89                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
90                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
91                                 /* 0x26256222 */
92 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
93                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
94                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
95                                 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
96                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
97                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
98                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
99                                 /* 0x029028c7 */
100 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
101                                 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
102                                 /* 0x03202000 */
103 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
104                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
105                                 | SDRAM_CFG_DBW_32)
106                                 /* 0x43080000 */
107 #define CONFIG_SYS_SDRAM_CFG2   0x00401000
108 #define CONFIG_SYS_DDR_MODE     ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
109                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
110                                 /* 0x44400232 */
111 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
112
113 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
114                                 /*0x02000000*/
115 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
116                                 | DDRCDR_PZ_NOMZ \
117                                 | DDRCDR_NZ_NOMZ \
118                                 | DDRCDR_M_ODR)
119                                 /* 0x73000002 */
120
121 /*
122  * FLASH on the Local Bus
123  */
124 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
125 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
126 #define CONFIG_SYS_FLASH_BASE           0xFE000000
127 #define CONFIG_SYS_FLASH_SIZE           32      /* size in MB */
128 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
129 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
130
131 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
132                                         | BR_PS_16      /* 16 bit */ \
133                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
134                                         | BR_V)         /* valid */
135 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
136                                         | OR_GPCM_CSNT \
137                                         | OR_GPCM_ACS_DIV4 \
138                                         | OR_GPCM_SCY_5 \
139                                         | OR_GPCM_TRLX_SET \
140                                         | OR_GPCM_EAD)
141                                         /* 0xfe000c55 */
142
143 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
144 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
145
146 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
147 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per dev */
148
149 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
150 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
151
152 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
153
154 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
155 #define CONFIG_SYS_RAMBOOT
156 #endif
157
158 #define CONFIG_SYS_INIT_RAM_LOCK        1
159 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
160 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
161
162 #define CONFIG_SYS_GBL_DATA_OFFSET      \
163                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
164 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
165
166 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
167 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)
168 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
169
170 /*
171  * Local Bus LCRR and LBCR regs
172  */
173 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_3
174 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_2
175
176 #define CONFIG_SYS_LBC_LBCR     0x00040000
177
178 #define CONFIG_SYS_LBC_MRTPR    0x20000000
179
180 /*
181  * NAND settings
182  */
183 #define CONFIG_SYS_NAND_BASE            0x61000000
184 #define CONFIG_SYS_MAX_NAND_DEVICE      1
185 #define CONFIG_CMD_NAND 1
186 #define CONFIG_NAND_FSL_ELBC 1
187 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
188
189 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
190                                         | BR_PS_8               \
191                                         | BR_DECC_CHK_GEN       \
192                                         | BR_MS_FCM             \
193                                         | BR_V) /* valid */
194                                         /* 0x61000c21 */
195 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB \
196                                         | OR_FCM_BCTLD \
197                                         | OR_FCM_CHT \
198                                         | OR_FCM_SCY_2 \
199                                         | OR_FCM_RST \
200                                         | OR_FCM_TRLX)
201                                         /* 0xffff90ac */
202
203 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
204 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
205 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
206 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
207
208 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
209 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
210
211 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
212 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
213
214 /* CS2 NvRAM */
215 #define CONFIG_SYS_BR2_PRELIM   (0x60000000 \
216                                 | BR_PS_8 \
217                                 | BR_V)
218                                 /* 0x60000801 */
219 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_128KB \
220                                 | OR_GPCM_CSNT \
221                                 | OR_GPCM_XACS \
222                                 | OR_GPCM_SCY_3 \
223                                 | OR_GPCM_TRLX_SET \
224                                 | OR_GPCM_EHTR_SET \
225                                 | OR_GPCM_EAD)
226                                 /* 0xfffe0937 */
227 /* local bus read write buffer mapping SRAM@0x64000000 */
228 #define CONFIG_SYS_BR3_PRELIM   (0x62000000 \
229                                 | BR_PS_16 \
230                                 | BR_V)
231                                 /* 0x62001001 */
232
233 #define CONFIG_SYS_OR3_PRELIM   (OR_AM_32MB \
234                                 | OR_GPCM_CSNT \
235                                 | OR_GPCM_XACS \
236                                 | OR_GPCM_SCY_15 \
237                                 | OR_GPCM_TRLX_SET \
238                                 | OR_GPCM_EHTR_SET \
239                                 | OR_GPCM_EAD)
240                                 /* 0xfe0009f7 */
241
242 /*
243  * Serial Port
244  */
245 #define CONFIG_CONS_INDEX       1
246 #define CONFIG_SYS_NS16550_SERIAL
247 #define CONFIG_SYS_NS16550_REG_SIZE     1
248 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
249
250 #define CONFIG_SYS_BAUDRATE_TABLE       \
251         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
252
253 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
254 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
255
256 #if defined(CONFIG_PCI)
257 /*
258  * General PCI
259  * Addresses are mapped 1-1.
260  */
261 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
262 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
263 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
264 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
265 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
266 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
267 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
268 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
269 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
270
271 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
272 #endif
273
274 /*
275  * TSEC
276  */
277 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
278
279 #define CONFIG_TSEC1
280 #ifdef CONFIG_TSEC1
281 #define CONFIG_HAS_ETH0
282 #define CONFIG_TSEC1_NAME       "TSEC1"
283 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
284 #define TSEC1_PHY_ADDR          0x01
285 #define TSEC1_FLAGS             0
286 #define TSEC1_PHYIDX            0
287 #endif
288
289 /* Options are: TSEC[0-1] */
290 #define CONFIG_ETHPRIME                 "TSEC1"
291
292 /*
293  * Environment
294  */
295 #define CONFIG_ENV_IS_IN_FLASH  1
296 #define CONFIG_ENV_ADDR         \
297                         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
298 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
299 #define CONFIG_ENV_SIZE         0x4000
300 /* Address and size of Redundant Environment Sector */
301 #define CONFIG_ENV_OFFSET_REDUND        \
302                         (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
303 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
304
305 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
306 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
307
308 /*
309  * BOOTP options
310  */
311 #define CONFIG_BOOTP_BOOTFILESIZE
312 #define CONFIG_BOOTP_BOOTPATH
313 #define CONFIG_BOOTP_GATEWAY
314 #define CONFIG_BOOTP_HOSTNAME
315
316 /*
317  * Command line configuration.
318  */
319 #define CONFIG_CMD_PCI
320
321 #define CONFIG_CMDLINE_EDITING 1
322 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
323
324 /*
325  * Miscellaneous configurable options
326  */
327 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
328 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
329 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
330
331 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
332 #define CONFIG_SYS_MAXARGS      16              /* max number of cmd args */
333 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
334
335 /*
336  * For booting Linux, the board info and command line data
337  * have to be in the first 256 MB of memory, since this is
338  * the maximum mapped by the Linux kernel during initialization.
339  */
340                                 /* Initial Memory map for Linux*/
341 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
342
343 /* 0x64050000 */
344 #define CONFIG_SYS_HRCW_LOW (\
345         0x20000000 /* reserved, must be set */ |\
346         HRCWL_DDRCM |\
347         HRCWL_CSB_TO_CLKIN_4X1 | \
348         HRCWL_CORE_TO_CSB_2_5X1)
349
350 /* 0xa0600004 */
351 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
352         HRCWH_PCI_ARBITER_ENABLE | \
353         HRCWH_CORE_ENABLE | \
354         HRCWH_FROM_0X00000100 | \
355         HRCWH_BOOTSEQ_DISABLE |\
356         HRCWH_SW_WATCHDOG_DISABLE |\
357         HRCWH_ROM_LOC_LOCAL_16BIT | \
358         HRCWH_TSEC1M_IN_MII | \
359         HRCWH_BIG_ENDIAN | \
360         HRCWH_LALE_EARLY)
361
362 /* System IO Config */
363 #define CONFIG_SYS_SICRH        (0x01000000 | \
364                                 SICRH_ETSEC2_B | \
365                                 SICRH_ETSEC2_C | \
366                                 SICRH_ETSEC2_D | \
367                                 SICRH_ETSEC2_E | \
368                                 SICRH_ETSEC2_F | \
369                                 SICRH_ETSEC2_G | \
370                                 SICRH_TSOBI1 | \
371                                 SICRH_TSOBI2)
372                                 /* 0x010fff03 */
373 #define CONFIG_SYS_SICRL        (SICRL_LBC | \
374                                 SICRL_SPI_A | \
375                                 SICRL_SPI_B | \
376                                 SICRL_SPI_C | \
377                                 SICRL_SPI_D | \
378                                 SICRL_ETSEC2_A)
379                                 /* 0x33fc0003) */
380
381 #define CONFIG_SYS_HID0_INIT    0x000000000
382 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
383                                  HID0_ENABLE_INSTRUCTION_CACHE)
384
385 #define CONFIG_SYS_HID2 HID2_HBE
386
387 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
388
389 /* DDR @ 0x00000000 */
390 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
391 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
392                                 | BATU_BL_256M \
393                                 | BATU_VS \
394                                 | BATU_VP)
395
396 #if defined(CONFIG_PCI)
397 /* PCI @ 0x80000000 */
398 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
399 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
400                                 | BATU_BL_256M \
401                                 | BATU_VS \
402                                 | BATU_VP)
403 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
404                                 | BATL_PP_RW \
405                                 | BATL_CACHEINHIBIT \
406                                 | BATL_GUARDEDSTORAGE)
407 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
408                                 | BATU_BL_256M \
409                                 | BATU_VS \
410                                 | BATU_VP)
411 #else
412 #define CONFIG_SYS_IBAT1L       (0)
413 #define CONFIG_SYS_IBAT1U       (0)
414 #define CONFIG_SYS_IBAT2L       (0)
415 #define CONFIG_SYS_IBAT2U       (0)
416 #endif
417
418 /* PCI2 not supported on 8313 */
419 #define CONFIG_SYS_IBAT3L       (0)
420 #define CONFIG_SYS_IBAT3U       (0)
421 #define CONFIG_SYS_IBAT4L       (0)
422 #define CONFIG_SYS_IBAT4U       (0)
423
424 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
425 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
426                                 | BATL_PP_RW \
427                                 | BATL_CACHEINHIBIT \
428                                 | BATL_GUARDEDSTORAGE)
429 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
430                                 | BATU_BL_256M \
431                                 | BATU_VS \
432                                 | BATU_VP)
433
434 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
435 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
436 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
437
438 /*  FPGA, SRAM, NAND @ 0x60000000 */
439 #define CONFIG_SYS_IBAT7L       (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
440 #define CONFIG_SYS_IBAT7U       (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
441
442 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
443 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
444 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
445 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
446 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
447 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
448 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
449 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
450 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
451 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
452 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
453 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
454 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
455 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
456 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
457 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
458
459 #define CONFIG_NETDEV           eth0
460
461 #define CONFIG_HOSTNAME         ve8313
462 #define CONFIG_UBOOTPATH        ve8313/u-boot.bin
463
464 #define CONFIG_BAUDRATE         115200
465
466 #define CONFIG_EXTRA_ENV_SETTINGS \
467         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
468         "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0"                 \
469         "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0"                    \
470         "u-boot_addr_r=100000\0"                                        \
471         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
472         "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE)        \
473                 " +${filesize};"        \
474         "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"    \
475         "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)     \
476         " ${filesize};"                                                 \
477         "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
478
479 #endif  /* __CONFIG_H */