abb57fe94c560ef0e044e8d3e647ddaa5cad668a
[platform/kernel/u-boot.git] / include / configs / ve8313.h
1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
3  *
4  * (C) Copyright 2010
5  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25 /*
26  * ve8313 board configuration file
27  */
28
29 #ifndef __CONFIG_H
30 #define __CONFIG_H
31
32 /*
33  * High Level Configuration Options
34  */
35 #define CONFIG_E300             1
36 #define CONFIG_MPC83xx          1
37 #define CONFIG_MPC831x          1
38 #define CONFIG_MPC8313          1
39 #define CONFIG_VE8313           1
40
41 #ifndef CONFIG_SYS_TEXT_BASE
42 #define CONFIG_SYS_TEXT_BASE    0xfe000000
43 #endif
44
45 #define CONFIG_PCI              1
46 #define CONFIG_FSL_ELBC         1
47
48 #define CONFIG_BOARD_EARLY_INIT_F       1
49
50 /*
51  * On-board devices
52  *
53  */
54 #define CONFIG_83XX_CLKIN       32000000        /* in Hz */
55
56 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
57
58 #define CONFIG_SYS_IMMR         0xE0000000
59
60 #define CONFIG_SYS_MEMTEST_START        0x00001000
61 #define CONFIG_SYS_MEMTEST_END          0x07000000
62
63 #define CONFIG_SYS_ACR_PIPE_DEP         3       /* Arbiter pipeline depth */
64 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count */
65
66 /*
67  * Device configurations
68  */
69
70 /*
71  * DDR Setup
72  */
73 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
74 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
75 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
76
77 /*
78  * Manually set up DDR parameters, as this board does not
79  * have the SPD connected to I2C.
80  */
81 #define CONFIG_SYS_DDR_SIZE             128             /* MB */
82 #define CONFIG_SYS_DDR_CONFIG           ( CSCONFIG_EN \
83                                 | CSCONFIG_AP \
84                                 | 0x00040000 /* TODO */ \
85                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
86                                 /* 0x80840102 */
87
88 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
89 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
90                                 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
91                                 | ( 3 << TIMING_CFG0_RRT_SHIFT ) \
92                                 | ( 2 << TIMING_CFG0_WWT_SHIFT ) \
93                                 | ( 7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
94                                 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
95                                 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
96                                 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
97                                 /* 0x0e720802 */
98 #define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
99                                 | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
100                                 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
101                                 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
102                                 | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
103                                 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
104                                 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
105                                 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
106                                 /* 0x26256222 */
107 #define CONFIG_SYS_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
108                                 | ( 5 << TIMING_CFG2_CPO_SHIFT ) \
109                                 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
110                                 | ( 1 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
111                                 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
112                                 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
113                                 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
114                                 /* 0x029028c7 */
115 #define CONFIG_SYS_DDR_INTERVAL ( ( 0x320 << SDRAM_INTERVAL_REFINT_SHIFT ) \
116                                 | ( 0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
117                                 /* 0x03202000 */
118 #define CONFIG_SYS_SDRAM_CFG            ( SDRAM_CFG_SREN \
119                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
120                                 | SDRAM_CFG_32_BE )
121                                 /* 0x43080000 */
122 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
123 #define CONFIG_SYS_DDR_MODE             ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
124                                 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
125                                 /* 0x44400232 */
126 #define CONFIG_SYS_DDR_MODE_2           0x8000C000
127
128 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
129                                 /*0x02000000*/
130 #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
131                                 | DDRCDR_PZ_NOMZ \
132                                 | DDRCDR_NZ_NOMZ \
133                                 | DDRCDR_M_ODR )
134                                 /* 0x73000002 */
135
136 /*
137  * FLASH on the Local Bus
138  */
139 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
140 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
141 #define CONFIG_SYS_FLASH_BASE           0xFE000000
142 #define CONFIG_SYS_FLASH_SIZE           32      /* size in MB */
143 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
144 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
145
146 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE | \
147                                 (2 << BR_PS_SHIFT) |    /* 16 bit */ \
148                                 BR_V)                   /* valid */
149 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
150                                 | OR_GPCM_CSNT \
151                                 | OR_GPCM_ACS_DIV4 \
152                                 | OR_GPCM_SCY_5 \
153                                 | OR_GPCM_TRLX \
154                                 | OR_GPCM_EAD)
155                                 /* 0xfe000c55 */
156
157 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
158 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018 /* 32 MB window size */
159
160 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
161 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per dev */
162
163 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
164 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
165
166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
167
168 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
169 #define CONFIG_SYS_RAMBOOT
170 #endif
171
172 #define CONFIG_SYS_INIT_RAM_LOCK        1
173 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
174 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000  /* Size of used area in RAM*/
175
176 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
177                                          GENERATED_GBL_DATA_SIZE)
178 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
179
180 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
181 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)
182 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
183
184 /*
185  * Local Bus LCRR and LBCR regs
186  */
187 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_3
188 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_2
189
190 #define CONFIG_SYS_LBC_LBCR     0x00040000
191
192 #define CONFIG_SYS_LBC_MRTPR    0x20000000
193
194 /*
195  * NAND settings
196  */
197 #define CONFIG_SYS_NAND_BASE            0x61000000
198 #define CONFIG_SYS_MAX_NAND_DEVICE      1
199 #define CONFIG_MTD_NAND_VERIFY_WRITE
200 #define CONFIG_CMD_NAND 1
201 #define CONFIG_NAND_FSL_ELBC 1
202 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
203
204 #define CONFIG_SYS_NAND_BR_PRELIM       ( CONFIG_SYS_NAND_BASE \
205                                 | BR_PS_8               \
206                                 | BR_DECC_CHK_GEN       \
207                                 | BR_MS_FCM             \
208                                 | BR_V )        /* valid */
209                                 /* 0x61000c21 */
210 #define CONFIG_SYS_NAND_OR_PRELIM       (0xffff8000 \
211                                 | OR_FCM_BCTLD \
212                                 | OR_FCM_CHT \
213                                 | OR_FCM_SCY_2 \
214                                 | OR_FCM_RST \
215                                 | OR_FCM_TRLX)
216                                 /* 0xffff90ac */
217
218 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
219 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
220 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
221 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
222
223 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
224 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E      /* 32KB  */
225
226 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
227 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
228
229 /* CS2 NvRAM */
230 #define CONFIG_SYS_BR2_PRELIM   (0x60000000     \
231                                 | BR_PS_8       \
232                                 | BR_V)
233                                 /* 0x60000801 */
234 #define CONFIG_SYS_OR2_PRELIM   (0xfffe0000     \
235                                 | OR_GPCM_CSNT  \
236                                 | OR_GPCM_XACS  \
237                                 | OR_GPCM_SCY_3 \
238                                 | OR_GPCM_TRLX \
239                                 | OR_GPCM_EHTR \
240                                 | OR_GPCM_EAD)
241                                 /* 0xfffe0937 */
242 /* local bus read write buffer mapping SRAM@0x64000000 */
243 #define CONFIG_SYS_BR3_PRELIM   (0x62000000     \
244                                 | BR_PS_16      \
245                                 | BR_V)
246                                 /* 0x62001001 */
247
248 #define CONFIG_SYS_OR3_PRELIM   (0xfe000000     \
249                                 | OR_GPCM_CSNT  \
250                                 | OR_GPCM_XACS  \
251                                 | OR_GPCM_SCY_15 \
252                                 | OR_GPCM_TRLX \
253                                 | OR_GPCM_EHTR \
254                                 | OR_GPCM_EAD)
255                                 /* 0xfe0009f7 */
256
257 /* pass open firmware flat tree */
258 #define CONFIG_OF_LIBFDT        1
259 #define CONFIG_OF_BOARD_SETUP   1
260 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
261
262 /*
263  * Serial Port
264  */
265 #define CONFIG_CONS_INDEX       1
266 #define CONFIG_SYS_NS16550
267 #define CONFIG_SYS_NS16550_SERIAL
268 #define CONFIG_SYS_NS16550_REG_SIZE     1
269 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
270
271 #define CONFIG_SYS_BAUDRATE_TABLE       \
272         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
273
274 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
275 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
276
277 /* Use the HUSH parser */
278 #define CONFIG_SYS_HUSH_PARSER
279 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
280
281 #if defined(CONFIG_PCI)
282 /*
283  * General PCI
284  * Addresses are mapped 1-1.
285  */
286 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
287 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
288 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
289 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
290 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
291 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
292 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
293 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
294 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
295
296 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
297 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
298 #endif
299
300 /*
301  * TSEC
302  */
303 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
304
305 #define CONFIG_NET_MULTI
306
307 #define CONFIG_TSEC1
308 #ifdef CONFIG_TSEC1
309 #define CONFIG_HAS_ETH0
310 #define CONFIG_TSEC1_NAME       "TSEC1"
311 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
312 #define TSEC1_PHY_ADDR          0x01
313 #define TSEC1_FLAGS             0
314 #define TSEC1_PHYIDX            0
315 #endif
316
317 /* Options are: TSEC[0-1] */
318 #define CONFIG_ETHPRIME                 "TSEC1"
319
320 /*
321  * Environment
322  */
323 #define CONFIG_ENV_IS_IN_FLASH  1
324 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + \
325                                         CONFIG_SYS_MONITOR_LEN)
326 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
327 #define CONFIG_ENV_SIZE         0x4000
328 /* Address and size of Redundant Environment Sector */
329 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
330                                         CONFIG_ENV_SECT_SIZE)
331 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
332
333 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
334 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
335
336 /*
337  * BOOTP options
338  */
339 #define CONFIG_BOOTP_BOOTFILESIZE
340 #define CONFIG_BOOTP_BOOTPATH
341 #define CONFIG_BOOTP_GATEWAY
342 #define CONFIG_BOOTP_HOSTNAME
343
344 /*
345  * Command line configuration.
346  */
347 #include <config_cmd_default.h>
348
349 #define CONFIG_CMD_DHCP
350 #define CONFIG_CMD_MII
351 #define CONFIG_CMD_PING
352 #define CONFIG_CMD_PCI
353
354 #define CONFIG_CMDLINE_EDITING 1
355 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
356
357 /*
358  * Miscellaneous configurable options
359  */
360 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
361 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
362 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
363 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
364
365 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
366 #define CONFIG_SYS_MAXARGS      16              /* max number of cmd args */
367 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
368 #define CONFIG_SYS_HZ           1000            /* 1ms ticks */
369
370 /*
371  * For booting Linux, the board info and command line data
372  * have to be in the first 256 MB of memory, since this is
373  * the maximum mapped by the Linux kernel during initialization.
374  */
375 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
376
377 /* 0x64050000 */
378 #define CONFIG_SYS_HRCW_LOW (\
379         0x20000000 /* reserved, must be set */ |\
380         HRCWL_DDRCM |\
381         HRCWL_CSB_TO_CLKIN_4X1 | \
382         HRCWL_CORE_TO_CSB_2_5X1)
383
384 /* 0xa0600004 */
385 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
386         HRCWH_PCI_ARBITER_ENABLE | \
387         HRCWH_CORE_ENABLE | \
388         HRCWH_FROM_0X00000100 | \
389         HRCWH_BOOTSEQ_DISABLE |\
390         HRCWH_SW_WATCHDOG_DISABLE |\
391         HRCWH_ROM_LOC_LOCAL_16BIT | \
392         HRCWH_TSEC1M_IN_MII | \
393         HRCWH_BIG_ENDIAN | \
394         HRCWH_LALE_EARLY)
395
396 /* System IO Config */
397 #define CONFIG_SYS_SICRH        (0x01000000 | \
398                                 SICRH_ETSEC2_B | \
399                                 SICRH_ETSEC2_C | \
400                                 SICRH_ETSEC2_D | \
401                                 SICRH_ETSEC2_E | \
402                                 SICRH_ETSEC2_F | \
403                                 SICRH_ETSEC2_G | \
404                                 SICRH_TSOBI1 | \
405                                 SICRH_TSOBI2)
406                                 /* 0x010fff03 */
407 #define CONFIG_SYS_SICRL        (SICRL_LBC | \
408                                 SICRL_SPI_A | \
409                                 SICRL_SPI_B | \
410                                 SICRL_SPI_C | \
411                                 SICRL_SPI_D | \
412                                 SICRL_ETSEC2_A)
413                                 /* 0x33fc0003) */
414
415 #define CONFIG_SYS_HID0_INIT    0x000000000
416 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
417                                  HID0_ENABLE_INSTRUCTION_CACHE)
418
419 #define CONFIG_SYS_HID2 HID2_HBE
420
421 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
422
423 /* DDR @ 0x00000000 */
424 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
425 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
426                                  BATU_VS | BATU_VP)
427
428 #if defined(CONFIG_PCI)
429 /* PCI @ 0x80000000 */
430 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
431 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
432                                 BATU_VS | BATU_VP)
433 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
434                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
435 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
436                                 BATU_VS | BATU_VP)
437 #else
438 #define CONFIG_SYS_IBAT1L       (0)
439 #define CONFIG_SYS_IBAT1U       (0)
440 #define CONFIG_SYS_IBAT2L       (0)
441 #define CONFIG_SYS_IBAT2U       (0)
442 #endif
443
444 /* PCI2 not supported on 8313 */
445 #define CONFIG_SYS_IBAT3L       (0)
446 #define CONFIG_SYS_IBAT3U       (0)
447 #define CONFIG_SYS_IBAT4L       (0)
448 #define CONFIG_SYS_IBAT4U       (0)
449
450 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
451 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
452                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
453 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | \
454                                 BATU_VP)
455
456 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
457 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
458 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
459
460 /*  FPGA, SRAM, NAND @ 0x60000000 */
461 #define CONFIG_SYS_IBAT7L       (0x60000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
462 #define CONFIG_SYS_IBAT7U       (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
463
464 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
465 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
466 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
467 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
468 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
469 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
470 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
471 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
472 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
473 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
474 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
475 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
476 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
477 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
478 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
479 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
480
481 #define CONFIG_NETDEV           eth0
482
483 #define CONFIG_HOSTNAME         ve8313
484 #define CONFIG_UBOOTPATH        ve8313/u-boot.bin
485
486 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
487 #define CONFIG_BAUDRATE         115200
488
489 #define XMK_STR(x)      #x
490 #define MK_STR(x)       XMK_STR(x)
491
492 #define CONFIG_EXTRA_ENV_SETTINGS \
493         "netdev=" MK_STR(CONFIG_NETDEV) "\0"                            \
494         "ethprime=" MK_STR(CONFIG_TSEC1_NAME) "\0"                      \
495         "u-boot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
496         "u-boot_addr_r=100000\0"                                        \
497         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
498         "update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
499         "erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
500         "cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \
501         " ${filesize};" \
502         "protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
503
504 #undef MK_STR
505 #undef XMK_STR
506
507 #endif  /* __CONFIG_H */