include/configs/vcoreiii.h

   1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
   2 /*
   3  * Copyright (c) 2018 Microsemi Corporation
   4  */
   5
   6 #ifndef __VCOREIII_H
   7 #define __VCOREIII_H
   8
   9 #include <linux/sizes.h>
  10
  11 /* Onboard devices */
  12
  13 #define CONFIG_SYS_MALLOC_LEN           0x100000
  14 #define CONFIG_SYS_LOAD_ADDR            0x00100000
  15 #define CONFIG_SYS_INIT_SP_OFFSET       0x400000
  16
  17 #if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL)
  18 #define CPU_CLOCK_RATE                  416666666 /* Clock for the MIPS core */
  19 #define CONFIG_SYS_MIPS_TIMER_FREQ      208333333
  20 #else
  21 #define CPU_CLOCK_RATE                  500000000 /* Clock for the MIPS core */
  22 #define CONFIG_SYS_MIPS_TIMER_FREQ      (CPU_CLOCK_RATE / 2)
  23 #endif
  24 #define CONFIG_SYS_NS16550_CLK          CONFIG_SYS_MIPS_TIMER_FREQ
  25
  26 #define CONFIG_BOARD_TYPES
  27
  28 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
  29 #define CONFIG_ENV_OFFSET               (1024 * 1024)
  30 #define CONFIG_ENV_SIZE                 (256 * 1024)
  31 #define CONFIG_ENV_SECT_SIZE            (256 * 1024)
  32
  33 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  34 #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
  35 #define CONFIG_ENV_OFFSET_REDUND      (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
  36
  37 #define CONFIG_ENV_SPI_MAX_HZ           0 /* This force to read from DT */
  38 #define CONFIG_ENV_SPI_MODE             0 /* This force to read from DT */
  39 #endif
  40
  41 #define CONFIG_SYS_SDRAM_BASE           0x80000000
  42 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
  43 #define CONFIG_SYS_SDRAM_SIZE           (128 * SZ_1M)
  44 #elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
  45 #define CONFIG_SYS_SDRAM_SIZE           (256 * SZ_1M)
  46 #elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
  47 #define CONFIG_SYS_SDRAM_SIZE           (512 * SZ_1M)
  48 #else
  49 #error Unknown DDR size - please add!
  50 #endif
  51
  52 #define CONFIG_CONS_INDEX               1
  53
  54 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  55 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M)
  56
  57 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  58
  59 #define CONFIG_BOARD_EARLY_INIT_R
  60 #if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
  61 #define VCOREIII_DEFAULT_MTD_ENV                    \
  62         "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"      \
  63         "mtdids="CONFIG_MTDIDS_DEFAULT"\0"
  64 #else
  65 #define VCOREIII_DEFAULT_MTD_ENV    /* Go away */
  66 #endif
  67
  68 #define CONFIG_SYS_BOOTM_LEN      (16 << 20)      /* Increase max gunzip size */
  69
  70 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  71         VCOREIII_DEFAULT_MTD_ENV                                        \
  72         "loadaddr=0x81000000\0"                                         \
  73         "spi_image_off=0x00100000\0"                                    \
  74         "console=ttyS0,115200\0"                                        \
  75         "setup=setenv bootargs console=${console} ${mtdparts}"          \
  76         "${bootargs_extra}\0"                                           \
  77         "spiboot=run setup; sf probe; sf read ${loadaddr}"              \
  78         "${spi_image_off} 0x600000; bootm ${loadaddr}\0"                \
  79         "ubootfile=u-boot.bin\0"                                        \
  80         "update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};"       \
  81         "sf erase UBoot 0x100000;"                                      \
  82         "sf write ${loadaddr} UBoot  ${filesize}\0"                     \
  83         "bootcmd=run spiboot\0"                                         \
  84         ""
  85 #endif                          /* __VCOREIII_H */