1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
3 * Copyright (c) 2018 Microsemi Corporation
9 #include <linux/sizes.h>
13 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
15 #if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL)
16 #define CPU_CLOCK_RATE 416666666 /* Clock for the MIPS core */
17 #define CONFIG_SYS_MIPS_TIMER_FREQ 208333333
19 #define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
20 #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
22 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
24 #define CONFIG_SYS_SDRAM_BASE 0x80000000
25 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
26 #define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
27 #elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
28 #define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M)
29 #elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
30 #define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M)
32 #error Unknown DDR size - please add!
35 #define CONFIG_EXTRA_ENV_SETTINGS \
36 "loadaddr=0x81000000\0" \
37 "spi_image_off=0x00100000\0" \
38 "console=ttyS0,115200\0" \
39 "setup=setenv bootargs console=${console} ${mtdparts}" \
40 "${bootargs_extra}\0" \
41 "spiboot=run setup; sf probe; sf read ${loadaddr}" \
42 "${spi_image_off} 0x600000; bootm ${loadaddr}\0" \
43 "ubootfile=u-boot.bin\0" \
44 "update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};" \
45 "sf erase UBoot 0x100000;" \
46 "sf write ${loadaddr} UBoot ${filesize}\0" \
47 "bootcmd=run spiboot\0" \
49 #endif /* __VCOREIII_H */