2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 /* U-boot - Common settings for UniPhier Family */
9 #ifndef __CONFIG_UNIPHIER_COMMON_H__
10 #define __CONFIG_UNIPHIER_COMMON_H__
12 #if defined(CONFIG_MACH_PH1_PRO4)
13 #define CONFIG_DDR_NUM_CH0 2
14 #define CONFIG_DDR_NUM_CH1 2
16 /* Physical start address of SDRAM */
17 #define CONFIG_SDRAM0_BASE 0x80000000
18 #define CONFIG_SDRAM0_SIZE 0x20000000
19 #define CONFIG_SDRAM1_BASE 0xa0000000
20 #define CONFIG_SDRAM1_SIZE 0x20000000
23 #if defined(CONFIG_MACH_PH1_LD4)
24 #define CONFIG_DDR_NUM_CH0 1
25 #define CONFIG_DDR_NUM_CH1 1
27 /* Physical start address of SDRAM */
28 #define CONFIG_SDRAM0_BASE 0x80000000
29 #define CONFIG_SDRAM0_SIZE 0x10000000
30 #define CONFIG_SDRAM1_BASE 0x90000000
31 #define CONFIG_SDRAM1_SIZE 0x10000000
34 #if defined(CONFIG_MACH_PH1_SLD8)
35 #define CONFIG_DDR_NUM_CH0 1
36 #define CONFIG_DDR_NUM_CH1 1
38 /* Physical start address of SDRAM */
39 #define CONFIG_SDRAM0_BASE 0x80000000
40 #define CONFIG_SDRAM0_SIZE 0x10000000
41 #define CONFIG_SDRAM1_BASE 0x90000000
42 #define CONFIG_SDRAM1_SIZE 0x10000000
45 #define CONFIG_I2C_EEPROM
46 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
49 * Support card address map
51 #if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
52 # define CONFIG_SUPPORT_CARD_BASE 0x03f00000
53 # define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
54 # define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
55 # define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
58 #if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
59 # define CONFIG_SUPPORT_CARD_BASE 0x08000000
60 # define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
61 # define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630)
62 # define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
65 #ifdef CONFIG_SYS_NS16550_SERIAL
66 #define CONFIG_SYS_NS16550
67 #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
68 #define CONFIG_SYS_NS16550_CLK 12288000
69 #define CONFIG_SYS_NS16550_REG_SIZE -2
72 /* TODO: move to Kconfig and device tree */
74 #define CONFIG_SYS_NS16550_SERIAL
77 #define CONFIG_SMC911X
79 #define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
80 #define CONFIG_SMC911X_32_BIT
82 /*-----------------------------------------------------------------------
83 * MMU and Cache Setting
84 *----------------------------------------------------------------------*/
86 /* Comment out the following to enable L1 cache */
87 /* #define CONFIG_SYS_ICACHE_OFF */
88 /* #define CONFIG_SYS_DCACHE_OFF */
90 #define CONFIG_SYS_CACHELINE_SIZE 32
92 /* Comment out the following to enable L2 cache */
93 #define CONFIG_UNIPHIER_L2CACHE_ON
95 #define CONFIG_DISPLAY_CPUINFO
96 #define CONFIG_DISPLAY_BOARDINFO
97 #define CONFIG_MISC_INIT_F
98 #define CONFIG_BOARD_EARLY_INIT_F
99 #define CONFIG_BOARD_EARLY_INIT_R
100 #define CONFIG_BOARD_LATE_INIT
102 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
104 #define CONFIG_TIMESTAMP
107 #define CONFIG_MTD_DEVICE
110 * uncomment the following to disable FLASH related code.
112 /* #define CONFIG_SYS_NO_FLASH */
114 #define CONFIG_FLASH_CFI_DRIVER
115 #define CONFIG_SYS_FLASH_CFI
117 #define CONFIG_SYS_MAX_FLASH_SECT 256
118 #define CONFIG_SYS_MONITOR_BASE 0
119 #define CONFIG_SYS_FLASH_BASE 0
122 * flash_toggle does not work for out supoort card.
123 * We need to use flash_status_poll.
125 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
127 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
129 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
131 /* serial console configuration */
132 #define CONFIG_BAUDRATE 115200
134 #define CONFIG_SYS_GENERIC_BOARD
136 #if !defined(CONFIG_SPL_BUILD)
137 #define CONFIG_USE_ARCH_MEMSET
138 #define CONFIG_USE_ARCH_MEMCPY
141 #define CONFIG_SYS_LONGHELP /* undef to save memory */
143 #define CONFIG_CMDLINE_EDITING /* add command line history */
144 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
145 /* Print Buffer Size */
146 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
147 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
148 /* Boot Argument Buffer Size */
149 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
151 #define CONFIG_CONS_INDEX 1
154 * For NAND booting the environment is embedded in the U-Boot image. Please take
155 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
157 /* #define CONFIG_ENV_IS_IN_NAND */
158 #define CONFIG_ENV_IS_NOWHERE
159 #define CONFIG_ENV_SIZE 0x2000
160 #define CONFIG_ENV_OFFSET 0x0
161 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
163 /* Time clock 1MHz */
164 #define CONFIG_SYS_TIMER_RATE 1000000
167 * By default, ARP timeout is 5 sec.
168 * The first ARP request does not seem to work.
169 * So we need to retry ARP request anyway.
170 * We want to shrink the interval until the second ARP request.
172 #define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
174 #define CONFIG_SYS_MAX_NAND_DEVICE 1
175 #define CONFIG_SYS_NAND_MAX_CHIPS 2
176 #define CONFIG_SYS_NAND_ONFI_DETECTION
178 #define CONFIG_NAND_DENALI_ECC_SIZE 1024
180 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000
181 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000
183 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
185 #define CONFIG_SYS_NAND_USE_FLASH_BBT
186 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
189 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
190 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
191 #define CONFIG_CMD_FAT
192 #define CONFIG_FAT_WRITE
193 #define CONFIG_DOS_PARTITION
195 /* memtest works on */
196 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
197 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
199 #define CONFIG_BOOTDELAY 3
200 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
201 #define CONFIG_AUTOBOOT_KEYED 1
202 #define CONFIG_AUTOBOOT_PROMPT \
203 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
204 #define CONFIG_AUTOBOOT_DELAY_STR "d"
205 #define CONFIG_AUTOBOOT_STOP_STR " "
208 * Network Configuration
210 #define CONFIG_SERVERIP 192.168.11.1
211 #define CONFIG_IPADDR 192.168.11.10
212 #define CONFIG_GATEWAYIP 192.168.11.1
213 #define CONFIG_NETMASK 255.255.255.0
215 #define CONFIG_LOADADDR 0x84000000
216 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
217 #define CONFIG_BOOTFILE "fit.itb"
219 #define CONFIG_CMDLINE_EDITING /* add command line history */
221 #define CONFIG_BOOTCOMMAND "run $bootmode"
223 #define CONFIG_ROOTPATH "/nfs/root/path"
224 #define CONFIG_NFSBOOTCOMMAND \
225 "setenv bootargs $bootargs root=/dev/nfs rw " \
226 "nfsroot=$serverip:$rootpath " \
227 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
230 #define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init"
232 #define CONFIG_EXTRA_ENV_SETTINGS \
234 "image_offset=0x00080000\0" \
235 "image_size=0x00f00000\0" \
237 "nandupdate=nand erase 0 0x100000 &&" \
238 "tftpboot u-boot-spl.bin &&" \
239 "nand write $loadaddr 0 0x10000 &&" \
240 "tftpboot u-boot-dtb.img &&" \
241 "nand write $loadaddr 0x10000 0xf0000\0" \
242 "norboot=run add_default_bootargs &&" \
243 "bootm $image_offset\0" \
244 "nandboot=run add_default_bootargs &&" \
245 "nand read $loadaddr $image_offset $image_size &&" \
247 "add_default_bootargs=setenv bootargs $bootargs" \
248 " console=ttyS0,$baudrate\0" \
250 /* Open Firmware flat tree */
251 #define CONFIG_OF_LIBFDT
253 #define CONFIG_HAVE_ARM_SECURE
255 /* Memory Size & Mapping */
256 #define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE
258 #if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
259 /* Thre is no memory hole */
260 #define CONFIG_NR_DRAM_BANKS 1
261 #define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
263 #define CONFIG_NR_DRAM_BANKS 2
264 #define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
267 #if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
268 #define CONFIG_SPL_TEXT_BASE 0x00040000
270 #if defined(CONFIG_MACH_PH1_PRO4)
271 #define CONFIG_SPL_TEXT_BASE 0x00100000
274 #define CONFIG_SPL_STACK (0x0ff08000)
275 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
277 #define CONFIG_PANIC_HANG
279 #define CONFIG_SPL_FRAMEWORK
280 #define CONFIG_SPL_SERIAL_SUPPORT
281 #define CONFIG_SPL_NAND_SUPPORT
283 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
284 #define CONFIG_SPL_LIBGENERIC_SUPPORT
286 #define CONFIG_SPL_BOARD_INIT
288 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
290 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000
292 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */