2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 /* U-boot - Common settings for UniPhier Family */
9 #ifndef __CONFIG_UNIPHIER_COMMON_H__
10 #define __CONFIG_UNIPHIER_COMMON_H__
12 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
13 #define CONFIG_DDR_NUM_CH0 2
14 #define CONFIG_DDR_NUM_CH1 1
15 #define CONFIG_DDR_NUM_CH2 1
17 /* Physical start address of SDRAM */
18 #define CONFIG_SDRAM0_BASE 0x80000000
19 #define CONFIG_SDRAM0_SIZE 0x20000000
20 #define CONFIG_SDRAM1_BASE 0xc0000000
21 #define CONFIG_SDRAM1_SIZE 0x20000000
22 #define CONFIG_SDRAM2_BASE 0xc0000000
23 #define CONFIG_SDRAM2_SIZE 0x10000000
26 #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
27 #define CONFIG_DDR_NUM_CH0 1
28 #define CONFIG_DDR_NUM_CH1 1
30 /* Physical start address of SDRAM */
31 #define CONFIG_SDRAM0_BASE 0x80000000
32 #define CONFIG_SDRAM0_SIZE 0x10000000
33 #define CONFIG_SDRAM1_BASE 0x90000000
34 #define CONFIG_SDRAM1_SIZE 0x10000000
37 #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
38 #define CONFIG_DDR_NUM_CH0 2
39 #define CONFIG_DDR_NUM_CH1 2
41 /* Physical start address of SDRAM */
42 #define CONFIG_SDRAM0_BASE 0x80000000
43 #define CONFIG_SDRAM0_SIZE 0x20000000
44 #define CONFIG_SDRAM1_BASE 0xa0000000
45 #define CONFIG_SDRAM1_SIZE 0x20000000
48 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
49 #define CONFIG_DDR_NUM_CH0 1
50 #define CONFIG_DDR_NUM_CH1 1
52 /* Physical start address of SDRAM */
53 #define CONFIG_SDRAM0_BASE 0x80000000
54 #define CONFIG_SDRAM0_SIZE 0x10000000
55 #define CONFIG_SDRAM1_BASE 0x90000000
56 #define CONFIG_SDRAM1_SIZE 0x10000000
59 #define CONFIG_I2C_EEPROM
60 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
62 #ifdef CONFIG_SYS_NS16550_SERIAL
63 #define CONFIG_SYS_NS16550
64 #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
65 #define CONFIG_SYS_NS16550_CLK 12288000
66 #define CONFIG_SYS_NS16550_REG_SIZE -2
69 /* TODO: move to Kconfig and device tree */
71 #define CONFIG_SYS_NS16550_SERIAL
74 #define CONFIG_SMC911X
76 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */
77 #define CONFIG_SMC911X_BASE 0
78 #define CONFIG_SMC911X_32_BIT
80 /*-----------------------------------------------------------------------
81 * MMU and Cache Setting
82 *----------------------------------------------------------------------*/
84 /* Comment out the following to enable L1 cache */
85 /* #define CONFIG_SYS_ICACHE_OFF */
86 /* #define CONFIG_SYS_DCACHE_OFF */
88 #define CONFIG_SYS_CACHELINE_SIZE 32
90 /* Comment out the following to enable L2 cache */
91 #define CONFIG_UNIPHIER_L2CACHE_ON
93 #define CONFIG_DISPLAY_CPUINFO
94 #define CONFIG_DISPLAY_BOARDINFO
95 #define CONFIG_MISC_INIT_F
96 #define CONFIG_BOARD_EARLY_INIT_F
97 #define CONFIG_BOARD_EARLY_INIT_R
98 #define CONFIG_BOARD_LATE_INIT
100 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
102 #define CONFIG_TIMESTAMP
105 #define CONFIG_MTD_DEVICE
108 * uncomment the following to disable FLASH related code.
110 /* #define CONFIG_SYS_NO_FLASH */
112 #define CONFIG_FLASH_CFI_DRIVER
113 #define CONFIG_SYS_FLASH_CFI
115 #define CONFIG_SYS_MAX_FLASH_SECT 256
116 #define CONFIG_SYS_MONITOR_BASE 0
117 #define CONFIG_SYS_FLASH_BASE 0
120 * flash_toggle does not work for out supoort card.
121 * We need to use flash_status_poll.
123 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
125 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
127 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
129 /* serial console configuration */
130 #define CONFIG_BAUDRATE 115200
132 #define CONFIG_SYS_GENERIC_BOARD
134 #if !defined(CONFIG_SPL_BUILD)
135 #define CONFIG_USE_ARCH_MEMSET
136 #define CONFIG_USE_ARCH_MEMCPY
139 #define CONFIG_SYS_LONGHELP /* undef to save memory */
141 #define CONFIG_CMDLINE_EDITING /* add command line history */
142 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
143 /* Print Buffer Size */
144 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
145 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
146 /* Boot Argument Buffer Size */
147 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
149 #define CONFIG_CONS_INDEX 1
152 * For NAND booting the environment is embedded in the U-Boot image. Please take
153 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
155 /* #define CONFIG_ENV_IS_IN_NAND */
156 #define CONFIG_ENV_IS_NOWHERE
157 #define CONFIG_ENV_SIZE 0x2000
158 #define CONFIG_ENV_OFFSET 0x0
159 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
161 /* Time clock 1MHz */
162 #define CONFIG_SYS_TIMER_RATE 1000000
165 * By default, ARP timeout is 5 sec.
166 * The first ARP request does not seem to work.
167 * So we need to retry ARP request anyway.
168 * We want to shrink the interval until the second ARP request.
170 #define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
172 #define CONFIG_SYS_MAX_NAND_DEVICE 1
173 #define CONFIG_SYS_NAND_MAX_CHIPS 2
174 #define CONFIG_SYS_NAND_ONFI_DETECTION
176 #define CONFIG_NAND_DENALI_ECC_SIZE 1024
178 #ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
179 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
180 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
182 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000
183 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000
186 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
188 #define CONFIG_SYS_NAND_USE_FLASH_BBT
189 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
192 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
193 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
194 #define CONFIG_CMD_FAT
195 #define CONFIG_FAT_WRITE
196 #define CONFIG_DOS_PARTITION
198 /* memtest works on */
199 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
200 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
202 #define CONFIG_BOOTDELAY 3
203 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
206 * Network Configuration
208 #define CONFIG_SERVERIP 192.168.11.1
209 #define CONFIG_IPADDR 192.168.11.10
210 #define CONFIG_GATEWAYIP 192.168.11.1
211 #define CONFIG_NETMASK 255.255.255.0
213 #define CONFIG_LOADADDR 0x84000000
214 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
216 #define CONFIG_CMDLINE_EDITING /* add command line history */
218 #define CONFIG_BOOTCOMMAND "run $bootmode"
220 #define CONFIG_ROOTPATH "/nfs/root/path"
221 #define CONFIG_NFSBOOTCOMMAND \
222 "setenv bootargs $bootargs root=/dev/nfs rw " \
223 "nfsroot=$serverip:$rootpath " \
224 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
228 #define CONFIG_BOOTFILE "fitImage"
229 #define LINUXBOOT_ENV_SETTINGS \
230 "fit_addr=0x00100000\0" \
231 "fit_addr_r=0x84100000\0" \
232 "fit_size=0x00f00000\0" \
233 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
234 "bootm $fit_addr\0" \
235 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
236 "bootm $fit_addr_r\0" \
237 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \
238 "bootm $fit_addr_r\0"
240 #define CONFIG_BOOTFILE "uImage"
241 #define LINUXBOOT_ENV_SETTINGS \
242 "fdt_addr=0x00100000\0" \
243 "fdt_addr_r=0x84100000\0" \
244 "fdt_size=0x00008000\0" \
245 "fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
246 "kernel_addr=0x00200000\0" \
247 "kernel_addr_r=0x84200000\0" \
248 "kernel_size=0x00800000\0" \
249 "ramdisk_addr=0x00a00000\0" \
250 "ramdisk_addr_r=0x84a00000\0" \
251 "ramdisk_size=0x00600000\0" \
252 "ramdisk_file=rootfs.cpio.uboot\0" \
253 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
254 "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
255 "setexpr fdt_addr $nor_base + $fdt_addr &&" \
256 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
257 "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
258 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
259 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
260 "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
261 "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
262 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \
263 "tftpboot $fdt_addr_r $fdt_file &&" \
264 "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
267 #define CONFIG_EXTRA_ENV_SETTINGS \
270 "norbase=0x42000000\0" \
271 "nandupdate=nand erase 0 0x00100000 &&" \
272 "tftpboot u-boot-spl-dtb.bin &&" \
273 "nand write $loadaddr 0 0x00010000 &&" \
274 "tftpboot u-boot-dtb.img &&" \
275 "nand write $loadaddr 0x00010000 0x000f0000\0" \
276 LINUXBOOT_ENV_SETTINGS
278 /* Open Firmware flat tree */
279 #define CONFIG_OF_LIBFDT
281 #define CONFIG_SYS_SDRAM_BASE 0x80000000
282 #define CONFIG_NR_DRAM_BANKS 2
284 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \
285 defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
286 defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
287 #define CONFIG_SPL_TEXT_BASE 0x00040000
289 #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
290 #define CONFIG_SPL_TEXT_BASE 0x00100000
293 #define CONFIG_SPL_STACK (0x0ff08000)
294 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
296 #define CONFIG_PANIC_HANG
298 #define CONFIG_SPL_FRAMEWORK
299 #define CONFIG_SPL_SERIAL_SUPPORT
300 #define CONFIG_SPL_NAND_SUPPORT
302 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
303 #define CONFIG_SPL_LIBGENERIC_SUPPORT
305 #define CONFIG_SPL_BOARD_INIT
307 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
309 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000
311 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */