ba89a425a8498c46e3b9c6e0a6809c9ce419f9c9
[platform/kernel/u-boot.git] / include / configs / uniphier.h
1 /*
2  * Copyright (C) 2012-2015 Panasonic Corporation
3  * Copyright (C) 2015      Socionext Inc.
4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 /* U-boot - Common settings for UniPhier Family */
10
11 #ifndef __CONFIG_UNIPHIER_COMMON_H__
12 #define __CONFIG_UNIPHIER_COMMON_H__
13
14 #if defined(CONFIG_MACH_PH1_PRO4)
15 #define CONFIG_DDR_NUM_CH0 2
16 #define CONFIG_DDR_NUM_CH1 2
17
18 /* Physical start address of SDRAM */
19 #define CONFIG_SDRAM0_BASE      0x80000000
20 #define CONFIG_SDRAM0_SIZE      0x20000000
21 #define CONFIG_SDRAM1_BASE      0xa0000000
22 #define CONFIG_SDRAM1_SIZE      0x20000000
23 #endif
24
25 #if defined(CONFIG_MACH_PH1_LD4)
26 #define CONFIG_DDR_NUM_CH0 1
27 #define CONFIG_DDR_NUM_CH1 1
28
29 /* Physical start address of SDRAM */
30 #define CONFIG_SDRAM0_BASE      0x80000000
31 #define CONFIG_SDRAM0_SIZE      0x10000000
32 #define CONFIG_SDRAM1_BASE      0x90000000
33 #define CONFIG_SDRAM1_SIZE      0x10000000
34 #endif
35
36 #if defined(CONFIG_MACH_PH1_SLD8)
37 #define CONFIG_DDR_NUM_CH0 1
38 #define CONFIG_DDR_NUM_CH1 1
39
40 /* Physical start address of SDRAM */
41 #define CONFIG_SDRAM0_BASE      0x80000000
42 #define CONFIG_SDRAM0_SIZE      0x10000000
43 #define CONFIG_SDRAM1_BASE      0x90000000
44 #define CONFIG_SDRAM1_SIZE      0x10000000
45 #endif
46
47 #define CONFIG_I2C_EEPROM
48 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10
49
50 /*
51  * Support card address map
52  */
53 #if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
54 # define CONFIG_SUPPORT_CARD_BASE       0x03f00000
55 # define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
56 # define CONFIG_SUPPORT_CARD_LED_BASE   (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
57 # define CONFIG_SUPPORT_CARD_UART_BASE  (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
58 #endif
59
60 #if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
61 # define CONFIG_SUPPORT_CARD_BASE       0x08000000
62 # define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
63 # define CONFIG_SUPPORT_CARD_LED_BASE   (CONFIG_SUPPORT_CARD_BASE + 0x00401630)
64 # define CONFIG_SUPPORT_CARD_UART_BASE  (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
65 #endif
66
67 #ifdef CONFIG_SYS_NS16550_SERIAL
68 #define CONFIG_SYS_NS16550
69 #define CONFIG_SYS_NS16550_COM1         CONFIG_SUPPORT_CARD_UART_BASE
70 #define CONFIG_SYS_NS16550_CLK          12288000
71 #define CONFIG_SYS_NS16550_REG_SIZE     -2
72 #endif
73
74 /* TODO: move to Kconfig and device tree */
75 #if 0
76 #define CONFIG_SYS_NS16550_SERIAL
77 #endif
78
79 #define CONFIG_SMC911X
80
81 #define CONFIG_SMC911X_BASE             CONFIG_SUPPORT_CARD_ETHER_BASE
82 #define CONFIG_SMC911X_32_BIT
83
84 /*-----------------------------------------------------------------------
85  * MMU and Cache Setting
86  *----------------------------------------------------------------------*/
87
88 /* Comment out the following to enable L1 cache */
89 /* #define CONFIG_SYS_ICACHE_OFF */
90 /* #define CONFIG_SYS_DCACHE_OFF */
91
92 #define CONFIG_SYS_CACHELINE_SIZE       32
93
94 /* Comment out the following to enable L2 cache */
95 #define CONFIG_UNIPHIER_L2CACHE_ON
96
97 #define CONFIG_DISPLAY_CPUINFO
98 #define CONFIG_DISPLAY_BOARDINFO
99 #define CONFIG_MISC_INIT_F
100 #define CONFIG_BOARD_EARLY_INIT_F
101 #define CONFIG_BOARD_EARLY_INIT_R
102 #define CONFIG_BOARD_LATE_INIT
103
104 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
105
106 #define CONFIG_TIMESTAMP
107
108 /* FLASH related */
109 #define CONFIG_MTD_DEVICE
110
111 /*
112  * uncomment the following to disable FLASH related code.
113  */
114 /* #define CONFIG_SYS_NO_FLASH */
115
116 #define CONFIG_FLASH_CFI_DRIVER
117 #define CONFIG_SYS_FLASH_CFI
118
119 #define CONFIG_SYS_MAX_FLASH_SECT       256
120 #define CONFIG_SYS_MONITOR_BASE         0
121 #define CONFIG_SYS_FLASH_BASE           0
122
123 /*
124  * flash_toggle does not work for out supoort card.
125  * We need to use flash_status_poll.
126  */
127 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
128
129 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
130
131 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
132
133 /* serial console configuration */
134 #define CONFIG_BAUDRATE                 115200
135
136 #define CONFIG_SYS_GENERIC_BOARD
137
138 #if !defined(CONFIG_SPL_BUILD)
139 #define CONFIG_USE_ARCH_MEMSET
140 #define CONFIG_USE_ARCH_MEMCPY
141 #endif
142
143 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
144
145 #define CONFIG_CMDLINE_EDITING          /* add command line history     */
146 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
147 /* Print Buffer Size */
148 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
149 #define CONFIG_SYS_MAXARGS              16      /* max number of command */
150 /* Boot Argument Buffer Size */
151 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
152
153 #define CONFIG_CONS_INDEX               1
154
155 /*
156  * For NAND booting the environment is embedded in the U-Boot image. Please take
157  * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
158  */
159 /* #define CONFIG_ENV_IS_IN_NAND */
160 #define CONFIG_ENV_IS_NOWHERE
161 #define CONFIG_ENV_SIZE                         0x2000
162 #define CONFIG_ENV_OFFSET                       0x0
163 /* #define CONFIG_ENV_OFFSET_REDUND     (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
164
165 /* Time clock 1MHz */
166 #define CONFIG_SYS_TIMER_RATE                   1000000
167
168 /*
169  * By default, ARP timeout is 5 sec.
170  * The first ARP request does not seem to work.
171  * So we need to retry ARP request anyway.
172  * We want to shrink the interval until the second ARP request.
173  */
174 #define CONFIG_ARP_TIMEOUT      500UL  /* 0.5 msec */
175
176 #define CONFIG_SYS_MAX_NAND_DEVICE                      1
177 #define CONFIG_SYS_NAND_MAX_CHIPS                       2
178 #define CONFIG_SYS_NAND_ONFI_DETECTION
179
180 #define CONFIG_NAND_DENALI_ECC_SIZE                     1024
181
182 #define CONFIG_SYS_NAND_REGS_BASE                       0x68100000
183 #define CONFIG_SYS_NAND_DATA_BASE                       0x68000000
184
185 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_DATA_BASE + 0x10)
186
187 #define CONFIG_SYS_NAND_USE_FLASH_BBT
188 #define CONFIG_SYS_NAND_BAD_BLOCK_POS                   0
189
190 /* USB */
191 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
192 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      4
193 #define CONFIG_CMD_FAT
194 #define CONFIG_FAT_WRITE
195 #define CONFIG_DOS_PARTITION
196
197 /* memtest works on */
198 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
199 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_SDRAM_BASE + 0x01000000)
200
201 #define CONFIG_BOOTDELAY                        3
202 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
203 #define CONFIG_AUTOBOOT_KEYED                   1
204 #define CONFIG_AUTOBOOT_PROMPT  \
205         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
206 #define CONFIG_AUTOBOOT_DELAY_STR               "d"
207 #define CONFIG_AUTOBOOT_STOP_STR                " "
208
209 /*
210  * Network Configuration
211  */
212 #define CONFIG_ETHADDR                  00:21:83:24:00:00
213 #define CONFIG_SERVERIP                 192.168.11.1
214 #define CONFIG_IPADDR                   192.168.11.10
215 #define CONFIG_GATEWAYIP                192.168.11.1
216 #define CONFIG_NETMASK                  255.255.255.0
217
218 #define CONFIG_LOADADDR                 0x84000000
219 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
220 #define CONFIG_BOOTFILE                 "fit.itb"
221
222 #define CONFIG_CMDLINE_EDITING          /* add command line history     */
223
224 #define CONFIG_BOOTCOMMAND              "run $bootmode"
225
226 #define CONFIG_ROOTPATH                 "/nfs/root/path"
227 #define CONFIG_NFSBOOTCOMMAND                                           \
228         "setenv bootargs $bootargs root=/dev/nfs rw "                   \
229         "nfsroot=$serverip:$rootpath "                                  \
230         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
231         "tftpboot; bootm;"
232
233 #define CONFIG_BOOTARGS         " user_debug=0x1f init=/sbin/init"
234
235 #define CONFIG_EXTRA_ENV_SETTINGS               \
236         "netdev=eth0\0"                         \
237         "image_offset=0x00080000\0"             \
238         "image_size=0x00f00000\0"               \
239         "verify=n\0"                            \
240         "nandupdate=nand erase 0 0x100000 &&"                           \
241                    "tftpboot u-boot-spl.bin &&"                         \
242                    "nand write $loadaddr 0 0x10000 &&"                  \
243                    "tftpboot u-boot-dtb.img &&"                         \
244                    "nand write $loadaddr 0x10000 0xf0000\0"             \
245         "norboot=run add_default_bootargs &&"                           \
246                 "bootm $image_offset\0"                                 \
247         "nandboot=run add_default_bootargs &&"                          \
248                  "nand read $loadaddr $image_offset $image_size &&"     \
249                  "bootm\0"                                              \
250         "add_default_bootargs=setenv bootargs $bootargs"                \
251                 " console=ttyS0,$baudrate\0"                            \
252
253 /* Open Firmware flat tree */
254 #define CONFIG_OF_LIBFDT
255
256 #define CONFIG_HAVE_ARM_SECURE
257
258 /* Memory Size & Mapping */
259 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SDRAM0_BASE
260
261 #if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
262 /* Thre is no memory hole */
263 #define CONFIG_NR_DRAM_BANKS            1
264 #define CONFIG_SYS_SDRAM_SIZE   (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
265 #else
266 #define CONFIG_NR_DRAM_BANKS            2
267 #define CONFIG_SYS_SDRAM_SIZE   (CONFIG_SDRAM0_SIZE)
268 #endif
269
270 #define CONFIG_SYS_TEXT_BASE            0x84000000
271
272 #if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
273 #define CONFIG_SPL_TEXT_BASE            0x00040000
274 #endif
275 #if defined(CONFIG_MACH_PH1_PRO4)
276 #define CONFIG_SPL_TEXT_BASE            0x00100000
277 #endif
278
279 #ifndef CONFIG_SPL_BUILD
280 #define CONFIG_SKIP_LOWLEVEL_INIT
281 #endif
282
283 #define CONFIG_SPL_STACK                (0x0ff08000)
284 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE)
285
286 #define CONFIG_PANIC_HANG
287
288 #define CONFIG_SPL_FRAMEWORK
289 #define CONFIG_SPL_SERIAL_SUPPORT
290 #define CONFIG_SPL_NAND_SUPPORT
291
292 #define CONFIG_SPL_LIBCOMMON_SUPPORT    /* for mem_malloc_init */
293 #define CONFIG_SPL_LIBGENERIC_SUPPORT
294
295 #define CONFIG_SPL_BOARD_INIT
296
297 #define CONFIG_SYS_NAND_U_BOOT_OFFS             0x10000
298
299 #define CONFIG_SPL_MAX_FOOTPRINT                0x10000
300
301 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */