2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 /* U-Boot - Common settings for UniPhier Family */
9 #ifndef __CONFIG_UNIPHIER_COMMON_H__
10 #define __CONFIG_UNIPHIER_COMMON_H__
12 #define CONFIG_I2C_EEPROM
13 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
15 #define CONFIG_SMC911X
17 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */
18 #define CONFIG_SMC911X_BASE 0
19 #define CONFIG_SMC911X_32_BIT
21 /*-----------------------------------------------------------------------
22 * MMU and Cache Setting
23 *----------------------------------------------------------------------*/
25 /* Comment out the following to enable L1 cache */
26 /* #define CONFIG_SYS_ICACHE_OFF */
27 /* #define CONFIG_SYS_DCACHE_OFF */
29 #define CONFIG_SYS_CACHELINE_SIZE 32
31 /* Comment out the following to disable L2 cache */
32 #define CONFIG_UNIPHIER_L2CACHE_ON
34 #define CONFIG_DISPLAY_CPUINFO
35 #define CONFIG_DISPLAY_BOARDINFO
36 #define CONFIG_MISC_INIT_F
37 #define CONFIG_BOARD_EARLY_INIT_F
38 #define CONFIG_BOARD_EARLY_INIT_R
39 #define CONFIG_BOARD_LATE_INIT
41 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
43 #define CONFIG_TIMESTAMP
46 #define CONFIG_MTD_DEVICE
49 * uncomment the following to disable FLASH related code.
51 /* #define CONFIG_SYS_NO_FLASH */
53 #define CONFIG_FLASH_CFI_DRIVER
54 #define CONFIG_SYS_FLASH_CFI
56 #define CONFIG_SYS_MAX_FLASH_SECT 256
57 #define CONFIG_SYS_MONITOR_BASE 0
58 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */
59 #define CONFIG_SYS_FLASH_BASE 0
62 * flash_toggle does not work for out supoort card.
63 * We need to use flash_status_poll.
65 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
67 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
69 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
71 /* serial console configuration */
72 #define CONFIG_BAUDRATE 115200
74 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
75 #define CONFIG_USE_ARCH_MEMSET
76 #define CONFIG_USE_ARCH_MEMCPY
79 #define CONFIG_SYS_LONGHELP /* undef to save memory */
81 #define CONFIG_CMDLINE_EDITING /* add command line history */
82 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
83 /* Print Buffer Size */
84 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
85 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
86 /* Boot Argument Buffer Size */
87 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
89 #define CONFIG_CONS_INDEX 1
91 /* #define CONFIG_ENV_IS_NOWHERE */
92 /* #define CONFIG_ENV_IS_IN_NAND */
93 #define CONFIG_ENV_IS_IN_MMC
94 #define CONFIG_ENV_OFFSET 0x80000
95 #define CONFIG_ENV_SIZE 0x2000
96 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
98 #define CONFIG_SYS_MMC_ENV_DEV 0
99 #define CONFIG_SYS_MMC_ENV_PART 1
102 #define CONFIG_ARMV8_MULTIENTRY
103 #define CPU_RELEASE_ADDR 0x80000100
104 #define COUNTER_FREQUENCY 50000000
106 #define GICD_BASE 0x5fe00000
107 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
108 #define GICR_BASE 0x5fe40000
109 #elif defined(CONFIG_ARCH_UNIPHIER_LD20)
110 #define GICR_BASE 0x5fe80000
113 /* Time clock 1MHz */
114 #define CONFIG_SYS_TIMER_RATE 1000000
118 #define CONFIG_SYS_MAX_NAND_DEVICE 1
119 #define CONFIG_SYS_NAND_MAX_CHIPS 2
120 #define CONFIG_SYS_NAND_ONFI_DETECTION
122 #define CONFIG_NAND_DENALI_ECC_SIZE 1024
124 #ifdef CONFIG_ARCH_UNIPHIER_SLD3
125 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
126 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
128 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000
129 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000
132 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
134 #define CONFIG_SYS_NAND_USE_FLASH_BBT
135 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
138 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
139 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
140 #define CONFIG_FAT_WRITE
141 #define CONFIG_DOS_PARTITION
144 #define CONFIG_SUPPORT_EMMC_BOOT
145 #define CONFIG_GENERIC_MMC
147 /* memtest works on */
148 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
149 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
151 #define CONFIG_BOOTDELAY 3
152 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
155 * Network Configuration
157 #define CONFIG_SERVERIP 192.168.11.1
158 #define CONFIG_IPADDR 192.168.11.10
159 #define CONFIG_GATEWAYIP 192.168.11.1
160 #define CONFIG_NETMASK 255.255.255.0
162 #define CONFIG_LOADADDR 0x84000000
163 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
165 #define CONFIG_CMDLINE_EDITING /* add command line history */
167 #define CONFIG_BOOTCOMMAND "run $bootmode"
169 #define CONFIG_ROOTPATH "/nfs/root/path"
170 #define CONFIG_NFSBOOTCOMMAND \
171 "setenv bootargs $bootargs root=/dev/nfs rw " \
172 "nfsroot=$serverip:$rootpath " \
173 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
177 #define CONFIG_BOOTFILE "fitImage"
178 #define LINUXBOOT_ENV_SETTINGS \
179 "fit_addr=0x00100000\0" \
180 "fit_addr_r=0x84100000\0" \
181 "fit_size=0x00f00000\0" \
182 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
183 "bootm $fit_addr\0" \
184 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
185 "bootm $fit_addr_r\0" \
186 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \
187 "bootm $fit_addr_r\0" \
188 "__nfsboot=run tftpboot\0"
191 #define CONFIG_CMD_BOOTI
192 #define CONFIG_BOOTFILE "Image"
193 #define LINUXBOOT_CMD "booti"
194 #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0"
195 #define KERNEL_SIZE "kernel_size=0x00c00000\0"
196 #define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0"
198 #define CONFIG_BOOTFILE "zImage"
199 #define LINUXBOOT_CMD "bootz"
200 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0"
201 #define KERNEL_SIZE "kernel_size=0x00800000\0"
202 #define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0"
204 #define LINUXBOOT_ENV_SETTINGS \
205 "fdt_addr=0x00100000\0" \
206 "fdt_addr_r=0x84100000\0" \
207 "fdt_size=0x00008000\0" \
208 "kernel_addr=0x00200000\0" \
212 "ramdisk_addr_r=0x84a00000\0" \
213 "ramdisk_size=0x00600000\0" \
214 "ramdisk_file=rootfs.cpio.uboot\0" \
215 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
216 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
217 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
218 "setexpr kernel_size $kernel_size / 4 &&" \
219 "cp $kernel_addr $kernel_addr_r $kernel_size &&" \
220 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
221 "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
222 "run boot_common\0" \
223 "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
224 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
225 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
226 "run boot_common\0" \
227 "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
228 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \
229 "tftpboot $fdt_addr_r $fdt_file &&" \
230 "run boot_common\0" \
231 "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
232 "tftpboot $fdt_addr_r $fdt_file &&" \
233 "tftpboot $fdt_addr_r $fdt_file &&" \
234 "setenv ramdisk_addr_r - &&" \
238 #define CONFIG_EXTRA_ENV_SETTINGS \
241 "nor_base=0x42000000\0" \
242 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
243 "tftpboot $tmp_addr u-boot-spl.bin &&" \
244 "setexpr tmp_addr $nor_base + 0x60000 &&" \
245 "tftpboot $tmp_addr u-boot.bin\0" \
246 "emmcupdate=mmcsetn &&" \
247 "mmc partconf $mmc_first_dev 0 1 1 &&" \
248 "mmc erase 0 800 &&" \
249 "tftpboot u-boot-spl.bin &&" \
250 "mmc write $loadaddr 0 80 &&" \
251 "tftpboot u-boot.bin &&" \
252 "mmc write $loadaddr 80 780\0" \
253 "nandupdate=nand erase 0 0x00100000 &&" \
254 "tftpboot u-boot-spl.bin &&" \
255 "nand write $loadaddr 0 0x00010000 &&" \
256 "tftpboot u-boot.bin &&" \
257 "nand write $loadaddr 0x00010000 0x000f0000\0" \
258 LINUXBOOT_ENV_SETTINGS
260 #define CONFIG_SYS_BOOTMAPSZ 0x20000000
262 #define CONFIG_SYS_SDRAM_BASE 0x80000000
263 #define CONFIG_NR_DRAM_BANKS 2
264 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */
265 #define CONFIG_SYS_MEM_TOP_HIDE 64
267 #if defined(CONFIG_ARM64)
268 #define CONFIG_SPL_TEXT_BASE 0x30000000
269 #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
270 defined(CONFIG_ARCH_UNIPHIER_LD4) || \
271 defined(CONFIG_ARCH_UNIPHIER_SLD8)
272 #define CONFIG_SPL_TEXT_BASE 0x00040000
274 #define CONFIG_SPL_TEXT_BASE 0x00100000
277 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
278 #define CONFIG_SPL_STACK (0x30014c00)
279 #elif defined(CONFIG_ARCH_UNIPHIER_LD20)
280 #define CONFIG_SPL_STACK (0x3001c000)
282 #define CONFIG_SPL_STACK (0x00100000)
284 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
286 #define CONFIG_PANIC_HANG
288 #define CONFIG_SPL_FRAMEWORK
289 #define CONFIG_SPL_SERIAL_SUPPORT
290 #define CONFIG_SPL_NOR_SUPPORT
292 #define CONFIG_SPL_NAND_SUPPORT
293 #define CONFIG_SPL_MMC_SUPPORT
296 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
297 #define CONFIG_SPL_LIBGENERIC_SUPPORT
299 #define CONFIG_SPL_BOARD_INIT
301 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
303 /* subtract sizeof(struct image_header) */
304 #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40)
305 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80
307 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
308 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000
309 #define CONFIG_SPL_MAX_SIZE 0x10000
310 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
311 #define CONFIG_SPL_BSS_START_ADDR 0x30012000
312 #elif defined(CONFIG_ARCH_UNIPHIER_LD20)
313 #define CONFIG_SPL_BSS_START_ADDR 0x30016000
315 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
317 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */