1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
15 * (C) Copyright 2010-2013
16 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
17 * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
24 * High Level Configuration Options
26 #define CONFIG_KM_BOARD_NAME "tuxx1"
27 #define CONFIG_HOSTNAME "tuxx1"
30 * High Level Configuration Options
32 #define CONFIG_QE /* Has QE */
33 #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
35 #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
37 /* include common defines/options for all 83xx Keymile boards */
38 #include "km83xx-common.h"
43 #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
46 * Hardware Reset Configuration Word
48 #define CONFIG_SYS_HRCW_LOW (\
49 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
50 HRCWL_DDR_TO_SCB_CLK_2X1 | \
51 HRCWL_CSB_TO_CLKIN_2X1 | \
52 HRCWL_CORE_TO_CSB_2_5X1 | \
53 HRCWL_CE_PLL_VCO_DIV_2 | \
56 #define CONFIG_SYS_HRCW_HIGH (\
58 HRCWH_PCI_ARBITER_DISABLE | \
60 HRCWH_FROM_0X00000100 | \
61 HRCWH_BOOTSEQ_DISABLE | \
62 HRCWH_SW_WATCHDOG_DISABLE | \
63 HRCWH_ROM_LOC_LOCAL_16BIT | \
67 #define CONFIG_SYS_DDRCDR (\
73 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
74 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
79 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
80 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
81 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
82 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
84 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
85 CSCONFIG_ODT_WR_CFG | \
86 CSCONFIG_ROW_BIT_13 | \
89 #define CONFIG_SYS_DDR_MODE 0x47860242
90 #define CONFIG_SYS_DDR_MODE2 0x8080c000
92 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
93 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
94 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
95 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
96 (0 << TIMING_CFG0_WWT_SHIFT) | \
97 (0 << TIMING_CFG0_RRT_SHIFT) | \
98 (0 << TIMING_CFG0_WRT_SHIFT) | \
99 (0 << TIMING_CFG0_RWT_SHIFT))
101 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
102 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
103 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
104 (3 << TIMING_CFG1_WRREC_SHIFT) | \
105 (7 << TIMING_CFG1_REFREC_SHIFT) | \
106 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
107 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
108 (3 << TIMING_CFG1_PRETOACT_SHIFT))
110 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
111 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
112 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
113 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
114 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
115 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
116 (5 << TIMING_CFG2_CPO_SHIFT))
118 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
120 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
121 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
124 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
127 * Local Bus Configuration & Clock Setup
129 #define CONFIG_SYS_LCRR_DBYP 0x80000000
130 #define CONFIG_SYS_LCRR_EADC 0x00010000
131 #define CONFIG_SYS_LCRR_CLKDIV 0x00000002
133 #define CONFIG_SYS_LBC_LBCR 0x00000000
138 #define CONFIG_SYS_IBAT7L (0)
139 #define CONFIG_SYS_IBAT7U (0)
140 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
141 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
143 #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
144 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
145 #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
146 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
149 * Init Local Bus Memory Controller:
151 * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2
152 * -----------------------------------------------------------------------------
153 * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE
154 * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit)
156 * Device on board (continued)
157 * Bank Bus Machine PortSz Size KMTEPR2
158 * -----------------------------------------------------------------------------
159 * 2 Local GPCM 8 bit 256MB NVRAM
160 * 3 Local GPCM 8 bit 256MB TEP2 (16 bit)
164 * Configuration for C2 on the local bus
166 /* Window base at flash base */
167 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
168 /* Window size: 256 MB */
169 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
171 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
176 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
181 OR_GPCM_EHTR_CLEAR | \
185 * Configuration for C3 on the local bus
187 /* Access window base at PINC3 base */
188 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
189 /* Window size: 256 MB */
190 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
192 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
197 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
204 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
211 /* APP1: icache cacheable, but dcache-inhibit and guarded */
212 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \
215 /* 512M should also include APP2... */
216 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \
220 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \
222 BATL_CACHEINHIBIT | \
224 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
226 /* APP2: icache cacheable, but dcache-inhibit and guarded */
227 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \
230 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \
234 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \
236 BATL_CACHEINHIBIT | \
238 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
240 #define CONFIG_SYS_IBAT7L (0)
241 #define CONFIG_SYS_IBAT7U (0)
242 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
243 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
245 #endif /* __CONFIG_H */