include/configs/tuxx1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2008
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  *
  15  * (C) Copyright 2010-2013
  16  * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
  17  * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #if defined(CONFIG_KMSUPX5)
  27 #define CONFIG_KM_BOARD_NAME    "kmsupx5"
  28 #define CONFIG_HOSTNAME         "kmsupx5"
  29 #elif defined(CONFIG_TUGE1)
  30 #define CONFIG_KM_BOARD_NAME    "tuge1"
  31 #define CONFIG_HOSTNAME         "tuge1"
  32 #elif defined(CONFIG_TUXX1)     /* TUXX1 board (tuxa1/tuda1) specific */
  33 #define CONFIG_KM_BOARD_NAME    "tuxx1"
  34 #define CONFIG_HOSTNAME         "tuxx1"
  35 #elif defined(CONFIG_KMOPTI2)
  36 #define CONFIG_KM_BOARD_NAME    "kmopti2"
  37 #define CONFIG_HOSTNAME         "kmopti2"
  38 #elif defined(CONFIG_KMTEPR2)
  39 #define CONFIG_KM_BOARD_NAME    "kmtepr2"
  40 #define CONFIG_HOSTNAME         "kmtepr2"
  41 #else
  42 #error ("Board not supported")
  43 #endif
  44
  45 /*
  46  * High Level Configuration Options
  47  */
  48 #define CONFIG_QE       /* Has QE */
  49 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
  50
  51 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
  52
  53 /* include common defines/options for all 83xx Keymile boards */
  54 #include "km83xx-common.h"
  55
  56 /*
  57  * System IO Config
  58  */
  59 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
  60
  61 /*
  62  * Hardware Reset Configuration Word
  63  */
  64 #define CONFIG_SYS_HRCW_LOW (\
  65         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
  66         HRCWL_DDR_TO_SCB_CLK_2X1 | \
  67         HRCWL_CSB_TO_CLKIN_2X1 | \
  68         HRCWL_CORE_TO_CSB_2_5X1 | \
  69         HRCWL_CE_PLL_VCO_DIV_2 | \
  70         HRCWL_CE_TO_PLL_1X3)
  71
  72 #define CONFIG_SYS_HRCW_HIGH (\
  73         HRCWH_PCI_AGENT | \
  74         HRCWH_PCI_ARBITER_DISABLE | \
  75         HRCWH_CORE_ENABLE | \
  76         HRCWH_FROM_0X00000100 | \
  77         HRCWH_BOOTSEQ_DISABLE | \
  78         HRCWH_SW_WATCHDOG_DISABLE | \
  79         HRCWH_ROM_LOC_LOCAL_16BIT | \
  80         HRCWH_BIG_ENDIAN | \
  81         HRCWH_LALE_NORMAL)
  82
  83 #define CONFIG_SYS_DDRCDR (\
  84         DDRCDR_EN | \
  85         DDRCDR_PZ_MAXZ | \
  86         DDRCDR_NZ_MAXZ | \
  87         DDRCDR_M_ODR)
  88
  89 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
  90 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  91                                          SDRAM_CFG_32_BE | \
  92                                          SDRAM_CFG_SREN | \
  93                                          SDRAM_CFG_HSE)
  94
  95 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  96 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  97 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  98                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
  99
 100 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 101                                          CSCONFIG_ODT_WR_CFG | \
 102                                          CSCONFIG_ROW_BIT_13 | \
 103                                          CSCONFIG_COL_BIT_10)
 104
 105 #define CONFIG_SYS_DDR_MODE     0x47860242
 106 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 107
 108 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 109                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 110                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 111                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 112                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 113                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 114                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 115                                  (0 << TIMING_CFG0_RWT_SHIFT))
 116
 117 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 118                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 119                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 120                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 121                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 122                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 123                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 124                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 125
 126 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 127                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 128                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 129                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 130                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 131                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 132                                  (5 << TIMING_CFG2_CPO_SHIFT))
 133
 134 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 135
 136 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 137 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 138
 139 /* EEprom support */
 140 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 141
 142 /*
 143  * Local Bus Configuration & Clock Setup
 144  */
 145 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 146 #define CONFIG_SYS_LCRR_EADC    0x00010000
 147 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 148
 149 #define CONFIG_SYS_LBC_LBCR     0x00000000
 150
 151 /*
 152  * MMU Setup
 153  */
 154 #define CONFIG_SYS_IBAT7L       (0)
 155 #define CONFIG_SYS_IBAT7U       (0)
 156 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 157 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 158
 159 #define CONFIG_SYS_APP1_BASE    0xA0000000    /* PAXG */
 160 #define CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
 161 #if defined(CONFIG_TUXX1) || defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2)
 162 #define CONFIG_SYS_APP2_BASE    0xB0000000    /* PINC3 */
 163 #define CONFIG_SYS_APP2_SIZE    256 /* Megabytes */
 164 #endif
 165
 166 /*
 167  * Init Local Bus Memory Controller:
 168  *                                    Device on board
 169  * Bank Bus     Machine PortSz Size   TUDA1  TUXA1  TUGE1   KMSUPX4 KMOPTI2
 170  * -----------------------------------------------------------------------------
 171  *  2   Local   GPCM    8 bit  256MB  PAXG   LPXF   PAXI    LPXF    PAXE
 172  *  3   Local   GPCM    8 bit  256MB  PINC3  PINC2  unused  unused  OPI2(16 bit)
 173  *
 174  *                                    Device on board (continued)
 175  * Bank Bus     Machine PortSz Size   KMTEPR2
 176  * -----------------------------------------------------------------------------
 177  *  2   Local   GPCM    8 bit  256MB  NVRAM
 178  *  3   Local   GPCM    8 bit  256MB  TEP2 (16 bit)
 179  */
 180
 181 #if defined(CONFIG_KMTEPRO2)
 182 /*
 183  * Configuration for C2 (NVRAM) on the local bus
 184  */
 185 #define CONFIG_SYS_LBLAWBAR2_PRELIM    CONFIG_SYS_APP1_BASE
 186 #define CONFIG_SYS_LBLAWAR2_PRELIM     (LBLAWAR_EN | LBLAWAR_256MB)
 187 #define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_APP1_BASE | \
 188                                 BR_PS_8 | \
 189                                 BR_MS_GPCM | \
 190                                 BR_V)
 191 #define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
 192                                 OR_GPCM_CSNT | \
 193                                 OR_GPCM_ACS_DIV2 | \
 194                                 OR_GPCM_XACS | \
 195                                 OR_GPCM_SCY_2 | \
 196                                 OR_GPCM_TRLX_SET | \
 197                                 OR_GPCM_EHTR_SET | \
 198                                 OR_GPCM_EAD)
 199 #else
 200 /*
 201  * Configuration for C2 on the local bus
 202  */
 203 /* Window base at flash base */
 204 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
 205 /* Window size: 256 MB */
 206 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 207
 208 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
 209                                  BR_PS_8 | \
 210                                  BR_MS_GPCM | \
 211                                  BR_V)
 212
 213 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
 214                                  OR_GPCM_CSNT | \
 215                                  OR_GPCM_ACS_DIV4 | \
 216                                  OR_GPCM_SCY_2 | \
 217                                  OR_GPCM_TRLX_SET | \
 218                                  OR_GPCM_EHTR_CLEAR | \
 219                                  OR_GPCM_EAD)
 220 #endif
 221
 222 #if defined(CONFIG_TUXX1)
 223 /*
 224  * Configuration for C3 on the local bus
 225  */
 226 /* Access window base at PINC3 base */
 227 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
 228 /* Window size: 256 MB */
 229 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 230
 231 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
 232                                  BR_PS_8 |              \
 233                                  BR_MS_GPCM |           \
 234                                  BR_V)
 235
 236 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 237                                  OR_GPCM_CSNT | \
 238                                  OR_GPCM_ACS_DIV2 | \
 239                                  OR_GPCM_SCY_2 | \
 240                                  OR_GPCM_TRLX_SET | \
 241                                  OR_GPCM_EHTR_CLEAR)
 242
 243 #define CONFIG_SYS_MAMR         (MxMR_GPL_x4DIS | \
 244                                  0x0000c000 | \
 245                                  MxMR_WLFx_2X)
 246 #endif
 247
 248 #if defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2)
 249 /*
 250  * Configuration for C3 on the local bus
 251  */
 252 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
 253 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 254 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
 255                                  BR_PS_16 |             \
 256                                  BR_MS_GPCM |           \
 257                                  BR_V)
 258 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 259                                  OR_GPCM_SCY_4 | \
 260                                  OR_GPCM_TRLX_CLEAR | \
 261                                  OR_GPCM_EHTR_CLEAR)
 262 #endif
 263
 264 /*
 265  * MMU Setup
 266  */
 267 /* APP1: icache cacheable, but dcache-inhibit and guarded */
 268 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | \
 269                                  BATL_PP_RW | \
 270                                  BATL_MEMCOHERENCE)
 271 /* 512M should also include APP2... */
 272 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | \
 273                                  BATU_BL_256M | \
 274                                  BATU_VS | \
 275                                  BATU_VP)
 276 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | \
 277                                  BATL_PP_RW | \
 278                                  BATL_CACHEINHIBIT | \
 279                                  BATL_GUARDEDSTORAGE)
 280 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 281
 282 #if defined(CONFIG_TUGE1) || defined(CONFIG_KMSUPX5)
 283 #define CONFIG_SYS_IBAT6L       (0)
 284 #define CONFIG_SYS_IBAT6U       (0)
 285 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 286 #else
 287 /* APP2:  icache cacheable, but dcache-inhibit and guarded */
 288 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | \
 289                                  BATL_PP_RW | \
 290                                  BATL_MEMCOHERENCE)
 291 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | \
 292                                  BATU_BL_256M | \
 293                                  BATU_VS | \
 294                                  BATU_VP)
 295 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | \
 296                                  BATL_PP_RW | \
 297                                  BATL_CACHEINHIBIT | \
 298                                  BATL_GUARDEDSTORAGE)
 299 #endif
 300 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 301
 302 #define CONFIG_SYS_IBAT7L       (0)
 303 #define CONFIG_SYS_IBAT7U       (0)
 304 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 305 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 306
 307 #endif /* __CONFIG_H */