2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
15 * Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
27 * High Level Configuration Options
29 #define CONFIG_QE /* Has QE */
30 #define CONFIG_MPC832x /* MPC832x CPU specific */
31 #define CONFIG_TUXA1 /* TUXA1 board specific */
32 #define CONFIG_HOSTNAME tuxa1
33 #define CONFIG_KM_BOARD_NAME "tuxa1"
35 #define CONFIG_SYS_TEXT_BASE 0xF0000000
36 #define CONFIG_KM_DEF_NETDEV \
39 #define CONFIG_KM_DEF_ROOTPATH \
40 "rootpath=/opt/eldk/ppc_8xx\0"
42 /* include common defines/options for all 83xx Keymile boards */
43 #include "km83xx-common.h"
45 #define CONFIG_MISC_INIT_R
50 #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
53 * Hardware Reset Configuration Word
55 #define CONFIG_SYS_HRCW_LOW (\
56 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
57 HRCWL_DDR_TO_SCB_CLK_2X1 | \
58 HRCWL_CSB_TO_CLKIN_2X1 | \
59 HRCWL_CORE_TO_CSB_2_5X1 | \
60 HRCWL_CE_PLL_VCO_DIV_2 | \
63 #define CONFIG_SYS_HRCW_HIGH (\
65 HRCWH_PCI_ARBITER_DISABLE | \
67 HRCWH_FROM_0X00000100 | \
68 HRCWH_BOOTSEQ_DISABLE | \
69 HRCWH_SW_WATCHDOG_DISABLE | \
70 HRCWH_ROM_LOC_LOCAL_16BIT | \
74 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
75 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
79 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
80 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
81 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
82 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
84 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
85 CSCONFIG_ODT_WR_CFG | \
86 CSCONFIG_ROW_BIT_13 | \
89 #define CONFIG_SYS_DDR_MODE 0x47860252
90 #define CONFIG_SYS_DDR_MODE2 0x8080c000
92 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
93 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
94 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
95 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
96 (0 << TIMING_CFG0_WWT_SHIFT) | \
97 (0 << TIMING_CFG0_RRT_SHIFT) | \
98 (0 << TIMING_CFG0_WRT_SHIFT) | \
99 (0 << TIMING_CFG0_RWT_SHIFT))
101 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
102 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
103 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
104 (2 << TIMING_CFG1_WRREC_SHIFT) | \
105 (6 << TIMING_CFG1_REFREC_SHIFT) | \
106 (2 << TIMING_CFG1_ACTTORW_SHIFT) | \
107 (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
108 (2 << TIMING_CFG1_PRETOACT_SHIFT))
110 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
111 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
112 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
113 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
114 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
115 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
116 (5 << TIMING_CFG2_CPO_SHIFT))
118 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
120 #define CONFIG_SYS_PIGGY_BASE 0xE8000000
121 #define CONFIG_SYS_PIGGY_SIZE 128
122 #define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */
123 #define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */
124 #define CONFIG_SYS_PINC2_BASE 0xB0000000 /* PINC2 */
125 #define CONFIG_SYS_PINC2_SIZE 256 /* Megabytes */
129 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
132 * Local Bus Configuration & Clock Setup
134 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
135 #define CONFIG_SYS_LBC_LBCR 0x00000000
138 * Init Local Bus Memory Controller:
140 * Bank Bus Machine PortSz Size Device
141 * ---- --- ------- ------ ----- ------
142 * 2 Local GPCM 8 bit 256MB LPXF
143 * 3 Local GPCM 8 bit 256MB PINC2
148 * LPXF on the local bus CS2
149 * Window base at flash base
150 * Window size: 256 MB
152 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE
153 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
155 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \
160 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \
165 (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
168 * PINC2 on the local bus CS3
169 * Access window base at PINC2 base
170 * Window size: 256 MB
172 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PINC2_BASE
173 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
175 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PINC2_BASE | \
180 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \
182 (OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \
183 (~OR_GPCM_XACS)) | /* XACS = 0 */ \
185 (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
188 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
195 /* LPXF: icache cacheable, but dcache-inhibit and guarded */
196 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
198 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
200 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
201 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
202 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
205 /* PCI MEM space: cacheable */
206 #define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
207 #define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
208 #define CFG_DBAT6L CFG_IBAT6L
209 #define CFG_DBAT6U CFG_IBAT6U
210 /* PCI MMIO space: cache-inhibit and guarded */
211 #define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
212 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
213 #define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
214 #define CFG_DBAT7L CFG_IBAT7L
215 #define CFG_DBAT7U CFG_IBAT7U
216 #else /* CONFIG_PCI */
218 /* PINC2: icache cacheable, but dcache-inhibit and guarded */
219 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
221 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \
223 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
224 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
225 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
227 #define CONFIG_SYS_IBAT7L (0)
228 #define CONFIG_SYS_IBAT7U (0)
229 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
230 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
231 #endif /* CONFIG_PCI */
233 #endif /* __CONFIG_H */