2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
15 * Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
27 * High Level Configuration Options
29 #define CONFIG_TUXA1 /* TUXA1 board specific */
30 #define CONFIG_HOSTNAME tuxa1
31 #define CONFIG_KM_BOARD_NAME "tuxa1"
33 #define CONFIG_SYS_TEXT_BASE 0xF0000000
35 /* include common defines/options for all 8321 Keymile boards */
36 #include "km/km8321-common.h"
38 #define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */
39 #define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */
40 #define CONFIG_SYS_PINC2_BASE 0xB0000000 /* PINC2 */
41 #define CONFIG_SYS_PINC2_SIZE 256 /* Megabytes */
44 * Init Local Bus Memory Controller:
46 * Bank Bus Machine PortSz Size Device
47 * ---- --- ------- ------ ----- ------
48 * 2 Local GPCM 8 bit 256MB LPXF
49 * 3 Local GPCM 8 bit 256MB PINC2
54 * LPXF on the local bus CS2
55 * Window base at flash base
58 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE
59 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
61 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \
66 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \
71 (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
74 * PINC2 on the local bus CS3
75 * Access window base at PINC2 base
78 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PINC2_BASE
79 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
81 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PINC2_BASE | \
86 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \
88 (OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \
89 (~OR_GPCM_XACS)) | /* XACS = 0 */ \
91 (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
94 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
101 /* LPXF: icache cacheable, but dcache-inhibit and guarded */
102 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
104 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
106 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
107 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
108 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
110 /* PINC2: icache cacheable, but dcache-inhibit and guarded */
111 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
113 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \
115 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
116 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
117 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
119 #define CONFIG_SYS_IBAT7L (0)
120 #define CONFIG_SYS_IBAT7U (0)
121 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
122 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
124 #endif /* __CONFIG_H */