1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
15 * (C) Copyright 2010-2013
16 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
17 * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
24 * High Level Configuration Options
26 #define CONFIG_KM_BOARD_NAME "tuge1"
27 #define CONFIG_HOSTNAME "tuge1"
30 * High Level Configuration Options
32 #define CONFIG_QE /* Has QE */
33 #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
35 #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
37 /* include common defines/options for all Keymile boards */
38 #include "km/keymile-common.h"
39 #include "km/km-powerpc.h"
44 #define CONFIG_83XX_CLKIN 66000000
45 #define CONFIG_SYS_CLK_FREQ 66000000
46 #define CONFIG_83XX_PCICLK 66000000
51 #define CONFIG_SYS_IMMR 0xE0000000
54 * Bus Arbitration Configuration Register (ACR)
56 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
57 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
58 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
59 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
64 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
65 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
66 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
68 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
69 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
70 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
72 #define CFG_83XX_DDR_USES_CS0
75 * Manually set up DDR parameters
78 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
83 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
84 #define CONFIG_SYS_FLASH_BASE 0xF0000000
86 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
87 #define CONFIG_SYS_RAMBOOT
90 /* Reserve 768 kB for Mon */
91 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
94 * Initial RAM Base Address Setup
96 #define CONFIG_SYS_INIT_RAM_LOCK
97 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
98 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
99 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
100 GENERATED_GBL_DATA_SIZE)
103 * Init Local Bus Memory Controller:
105 * Bank Bus Machine PortSz Size Device
106 * ---- --- ------- ------ ----- ------
107 * 0 Local GPCM 16 bit 256MB FLASH
108 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
112 * FLASH on the Local Bus
114 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
116 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
117 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
119 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
120 BR_PS_16 | /* 16 bit port size */ \
121 BR_MS_GPCM | /* MSEL = GPCM */ \
124 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
125 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
127 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
129 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
130 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
131 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
134 * PRIO1/PIGGY on the local bus CS1
136 /* Window base at flash base */
137 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
138 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
140 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
141 BR_PS_8 | /* 8 bit port size */ \
142 BR_MS_GPCM | /* MSEL = GPCM */ \
144 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
145 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
147 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
152 #define CONFIG_SYS_NS16550_SERIAL
153 #define CONFIG_SYS_NS16550_REG_SIZE 1
154 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
156 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
157 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
160 * QE UEC ethernet configuration
162 #define CONFIG_UEC_ETH
163 #define CONFIG_ETHPRIME "UEC0"
165 #define CONFIG_UEC_ETH1 /* GETH1 */
166 #define UEC_VERBOSE_DEBUG 1
168 #ifdef CONFIG_UEC_ETH1
169 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
170 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
171 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
172 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
173 #define CONFIG_SYS_UEC1_PHY_ADDR 0
174 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
175 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
182 #ifndef CONFIG_SYS_RAMBOOT
183 #ifndef CONFIG_ENV_ADDR
184 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
185 CONFIG_SYS_MONITOR_LEN)
187 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
188 #ifndef CONFIG_ENV_OFFSET
189 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
192 /* Address and size of Redundant Environment Sector */
193 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
194 CONFIG_ENV_SECT_SIZE)
195 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
197 #else /* CFG_SYS_RAMBOOT */
198 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
199 #define CONFIG_ENV_SIZE 0x2000
200 #endif /* CFG_SYS_RAMBOOT */
203 #define CONFIG_SYS_I2C
204 #define CONFIG_SYS_NUM_I2C_BUSES 4
205 #define CONFIG_SYS_I2C_MAX_HOPS 1
206 #define CONFIG_SYS_I2C_FSL
207 #define CONFIG_SYS_FSL_I2C_SPEED 200000
208 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
209 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
210 #define CONFIG_SYS_I2C_OFFSET 0x3000
211 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
212 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
213 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
214 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
215 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
216 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
217 {1, {I2C_NULL_HOP} } }
219 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
221 #if defined(CONFIG_CMD_NAND)
222 #define CONFIG_NAND_KMETER1
223 #define CONFIG_SYS_MAX_NAND_DEVICE 1
224 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
228 * For booting Linux, the board info and command line data
229 * have to be in the first 8 MB of memory, since this is
230 * the maximum mapped by the Linux kernel during initialization.
232 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
237 #define CONFIG_SYS_HID0_INIT 0x000000000
238 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
239 HID0_ENABLE_INSTRUCTION_CACHE)
240 #define CONFIG_SYS_HID2 HID2_HBE
246 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
248 /* DDR: cache cacheable */
249 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
250 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
251 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
253 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
254 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
256 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
257 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
258 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
259 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
261 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
262 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
264 /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
265 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
267 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
269 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
270 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
271 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
273 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
274 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
276 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
278 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
279 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
280 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
282 /* Stack in dcache: cacheable, no memory coherence */
283 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
284 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
286 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
287 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
290 * Internal Definitions
292 #define BOOTFLASH_START 0xF0000000
294 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
297 * Environment Configuration
299 #define CONFIG_ENV_OVERWRITE
300 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
301 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
304 #ifndef CONFIG_KM_DEF_ARCH
305 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
308 #define CONFIG_EXTRA_ENV_SETTINGS \
312 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
313 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
317 #if defined(CONFIG_UEC_ETH)
318 #define CONFIG_HAS_ETH0
324 #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
327 * Hardware Reset Configuration Word
329 #define CONFIG_SYS_HRCW_LOW (\
330 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
331 HRCWL_DDR_TO_SCB_CLK_2X1 | \
332 HRCWL_CSB_TO_CLKIN_2X1 | \
333 HRCWL_CORE_TO_CSB_2_5X1 | \
334 HRCWL_CE_PLL_VCO_DIV_2 | \
337 #define CONFIG_SYS_HRCW_HIGH (\
339 HRCWH_PCI_ARBITER_DISABLE | \
340 HRCWH_CORE_ENABLE | \
341 HRCWH_FROM_0X00000100 | \
342 HRCWH_BOOTSEQ_DISABLE | \
343 HRCWH_SW_WATCHDOG_DISABLE | \
344 HRCWH_ROM_LOC_LOCAL_16BIT | \
348 #define CONFIG_SYS_DDRCDR (\
354 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
355 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
360 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
361 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
362 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
363 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
365 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
366 CSCONFIG_ODT_WR_CFG | \
367 CSCONFIG_ROW_BIT_13 | \
370 #define CONFIG_SYS_DDR_MODE 0x47860242
371 #define CONFIG_SYS_DDR_MODE2 0x8080c000
373 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
374 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
375 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
376 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
377 (0 << TIMING_CFG0_WWT_SHIFT) | \
378 (0 << TIMING_CFG0_RRT_SHIFT) | \
379 (0 << TIMING_CFG0_WRT_SHIFT) | \
380 (0 << TIMING_CFG0_RWT_SHIFT))
382 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
383 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
384 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
385 (3 << TIMING_CFG1_WRREC_SHIFT) | \
386 (7 << TIMING_CFG1_REFREC_SHIFT) | \
387 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
388 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
389 (3 << TIMING_CFG1_PRETOACT_SHIFT))
391 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
392 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
393 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
394 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
395 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
396 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
397 (5 << TIMING_CFG2_CPO_SHIFT))
399 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
401 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
402 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
405 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
408 * Local Bus Configuration & Clock Setup
410 #define CONFIG_SYS_LCRR_DBYP 0x80000000
411 #define CONFIG_SYS_LCRR_EADC 0x00010000
412 #define CONFIG_SYS_LCRR_CLKDIV 0x00000002
414 #define CONFIG_SYS_LBC_LBCR 0x00000000
419 #define CONFIG_SYS_IBAT7L (0)
420 #define CONFIG_SYS_IBAT7U (0)
421 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
422 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
424 #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
425 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
428 * Init Local Bus Memory Controller:
430 * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2
431 * -----------------------------------------------------------------------------
432 * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE
433 * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit)
435 * Device on board (continued)
436 * Bank Bus Machine PortSz Size KMTEPR2
437 * -----------------------------------------------------------------------------
438 * 2 Local GPCM 8 bit 256MB NVRAM
439 * 3 Local GPCM 8 bit 256MB TEP2 (16 bit)
443 * Configuration for C2 on the local bus
445 /* Window base at flash base */
446 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
447 /* Window size: 256 MB */
448 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
450 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
455 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
460 OR_GPCM_EHTR_CLEAR | \
466 /* APP1: icache cacheable, but dcache-inhibit and guarded */
467 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \
470 /* 512M should also include APP2... */
471 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \
475 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \
477 BATL_CACHEINHIBIT | \
479 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
481 #define CONFIG_SYS_IBAT6L (0)
482 #define CONFIG_SYS_IBAT6U (0)
483 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
484 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
486 #define CONFIG_SYS_IBAT7L (0)
487 #define CONFIG_SYS_IBAT7U (0)
488 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
489 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
491 #endif /* __CONFIG_H */