include/configs/tuge1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2008
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  *
  15  * (C) Copyright 2010-2013
  16  * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
  17  * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_KM_BOARD_NAME    "tuge1"
  27 #define CONFIG_HOSTNAME         "tuge1"
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_QE       /* Has QE */
  33 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
  34
  35 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
  36
  37 /* include common defines/options for all Keymile boards */
  38 #include "km/keymile-common.h"
  39 #include "km/km-powerpc.h"
  40
  41 /*
  42  * System Clock Setup
  43  */
  44 #define CONFIG_83XX_CLKIN               66000000
  45 #define CONFIG_SYS_CLK_FREQ             66000000
  46 #define CONFIG_83XX_PCICLK              66000000
  47
  48 /*
  49  * DDR Setup
  50  */
  51 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
  52 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  53
  54 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_SDRAM_BASE
  55 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  56                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  57
  58 #define CFG_83XX_DDR_USES_CS0
  59
  60 /*
  61  * Manually set up DDR parameters
  62  */
  63 #define CONFIG_DDR_II
  64 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  65
  66 /*
  67  * The reserved memory
  68  */
  69 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  70 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  71
  72 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  73 #define CONFIG_SYS_RAMBOOT
  74 #endif
  75
  76 /* Reserve 768 kB for Mon */
  77 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  78
  79 /*
  80  * Initial RAM Base Address Setup
  81  */
  82 #define CONFIG_SYS_INIT_RAM_LOCK
  83 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  84 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  85 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  86                                                 GENERATED_GBL_DATA_SIZE)
  87
  88 /*
  89  * Init Local Bus Memory Controller:
  90  *
  91  * Bank Bus     Machine PortSz  Size  Device
  92  * ---- ---     ------- ------  -----  ------
  93  *  0   Local   GPCM    16 bit  256MB FLASH
  94  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
  95  *
  96  */
  97 /*
  98  * FLASH on the Local Bus
  99  */
 100 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 101
 102
 103 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 104 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 105 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 106
 107 /*
 108  * PRIO1/PIGGY on the local bus CS1
 109  */
 110
 111
 112 /*
 113  * Serial Port
 114  */
 115 #define CONFIG_SYS_NS16550_SERIAL
 116 #define CONFIG_SYS_NS16550_REG_SIZE     1
 117 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 118
 119 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 120 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 121
 122 /*
 123  * QE UEC ethernet configuration
 124  */
 125 #define CONFIG_UEC_ETH
 126 #define CONFIG_ETHPRIME         "UEC0"
 127
 128 #define CONFIG_UEC_ETH1         /* GETH1 */
 129 #define UEC_VERBOSE_DEBUG       1
 130
 131 #ifdef CONFIG_UEC_ETH1
 132 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 133 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 134 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 135 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 136 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 137 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 138 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 139 #endif
 140
 141 /*
 142  * Environment
 143  */
 144
 145 #ifndef CONFIG_SYS_RAMBOOT
 146 #ifndef CONFIG_ENV_ADDR
 147 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 148                                         CONFIG_SYS_MONITOR_LEN)
 149 #endif
 150 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 151 #ifndef CONFIG_ENV_OFFSET
 152 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 153 #endif
 154
 155 /* Address and size of Redundant Environment Sector     */
 156 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 157                                                 CONFIG_ENV_SECT_SIZE)
 158 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 159
 160 #else /* CFG_SYS_RAMBOOT */
 161 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 162 #define CONFIG_ENV_SIZE         0x2000
 163 #endif /* CFG_SYS_RAMBOOT */
 164
 165 /* I2C */
 166 #define CONFIG_SYS_I2C
 167 #define CONFIG_SYS_NUM_I2C_BUSES        4
 168 #define CONFIG_SYS_I2C_MAX_HOPS         1
 169 #define CONFIG_SYS_I2C_FSL
 170 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 171 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 172 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 173 #define CONFIG_SYS_I2C_OFFSET           0x3000
 174 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 175 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 176 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 177 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 178                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 179                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 180                 {1, {I2C_NULL_HOP} } }
 181
 182 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 183
 184 #if defined(CONFIG_CMD_NAND)
 185 #define CONFIG_NAND_KMETER1
 186 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 187 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 188 #endif
 189
 190 /*
 191  * For booting Linux, the board info and command line data
 192  * have to be in the first 8 MB of memory, since this is
 193  * the maximum mapped by the Linux kernel during initialization.
 194  */
 195 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 196
 197 /*
 198  * Internal Definitions
 199  */
 200 #define BOOTFLASH_START 0xF0000000
 201
 202 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 203
 204 /*
 205  * Environment Configuration
 206  */
 207 #define CONFIG_ENV_OVERWRITE
 208 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 209 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 210 #endif
 211
 212 #ifndef CONFIG_KM_DEF_ARCH
 213 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 214 #endif
 215
 216 #define CONFIG_EXTRA_ENV_SETTINGS \
 217         CONFIG_KM_DEF_ENV                                               \
 218         CONFIG_KM_DEF_ARCH                                              \
 219         "newenv="                                                       \
 220                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 221                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 222         "unlock=yes\0"                                                  \
 223         ""
 224
 225 #if defined(CONFIG_UEC_ETH)
 226 #define CONFIG_HAS_ETH0
 227 #endif
 228
 229 /*
 230  * System IO Config
 231  */
 232 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
 233
 234 #define CONFIG_SYS_DDRCDR (\
 235         DDRCDR_EN | \
 236         DDRCDR_PZ_MAXZ | \
 237         DDRCDR_NZ_MAXZ | \
 238         DDRCDR_M_ODR)
 239
 240 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 241 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 242                                          SDRAM_CFG_32_BE | \
 243                                          SDRAM_CFG_SREN | \
 244                                          SDRAM_CFG_HSE)
 245
 246 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 247 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 248 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 249                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 250
 251 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 252                                          CSCONFIG_ODT_WR_CFG | \
 253                                          CSCONFIG_ROW_BIT_13 | \
 254                                          CSCONFIG_COL_BIT_10)
 255
 256 #define CONFIG_SYS_DDR_MODE     0x47860242
 257 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 258
 259 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 260                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 261                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 262                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 263                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 264                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 265                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 266                                  (0 << TIMING_CFG0_RWT_SHIFT))
 267
 268 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 269                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 270                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 271                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 272                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 273                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 274                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 275                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 276
 277 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 278                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 279                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 280                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 281                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 282                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 283                                  (5 << TIMING_CFG2_CPO_SHIFT))
 284
 285 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 286
 287 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 288 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 289
 290 /* EEprom support */
 291 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 292
 293 /*
 294  * Local Bus Configuration & Clock Setup
 295  */
 296 #define CONFIG_SYS_LBC_LBCR     0x00000000
 297
 298 #define CONFIG_SYS_APP1_BASE    0xA0000000    /* PAXG */
 299 #define CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
 300
 301 /*
 302  * Init Local Bus Memory Controller:
 303  *                                    Device on board
 304  * Bank Bus     Machine PortSz Size   TUDA1  TUXA1  TUGE1   KMSUPX4 KMOPTI2
 305  * -----------------------------------------------------------------------------
 306  *  2   Local   GPCM    8 bit  256MB  PAXG   LPXF   PAXI    LPXF    PAXE
 307  *  3   Local   GPCM    8 bit  256MB  PINC3  PINC2  unused  unused  OPI2(16 bit)
 308  *
 309  *                                    Device on board (continued)
 310  * Bank Bus     Machine PortSz Size   KMTEPR2
 311  * -----------------------------------------------------------------------------
 312  *  2   Local   GPCM    8 bit  256MB  NVRAM
 313  *  3   Local   GPCM    8 bit  256MB  TEP2 (16 bit)
 314  */
 315
 316
 317 #endif /* __CONFIG_H */