1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
15 * (C) Copyright 2010-2013
16 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
17 * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
24 * High Level Configuration Options
26 #define CONFIG_KM_BOARD_NAME "tuge1"
27 #define CONFIG_HOSTNAME "tuge1"
30 * High Level Configuration Options
32 #define CONFIG_QE /* Has QE */
33 #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
35 #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
37 /* include common defines/options for all Keymile boards */
38 #include "km/keymile-common.h"
39 #include "km/km-powerpc.h"
44 #define CONFIG_83XX_CLKIN 66000000
45 #define CONFIG_SYS_CLK_FREQ 66000000
46 #define CONFIG_83XX_PCICLK 66000000
51 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
52 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
54 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
55 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
57 #define CFG_83XX_DDR_USES_CS0
60 * Manually set up DDR parameters
63 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
68 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
69 #define CONFIG_SYS_FLASH_BASE 0xF0000000
71 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
72 #define CONFIG_SYS_RAMBOOT
75 /* Reserve 768 kB for Mon */
76 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
79 * Initial RAM Base Address Setup
81 #define CONFIG_SYS_INIT_RAM_LOCK
82 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
83 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
84 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
85 GENERATED_GBL_DATA_SIZE)
88 * Init Local Bus Memory Controller:
90 * Bank Bus Machine PortSz Size Device
91 * ---- --- ------- ------ ----- ------
92 * 0 Local GPCM 16 bit 256MB FLASH
93 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
97 * FLASH on the Local Bus
99 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
102 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
103 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
104 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
107 * PRIO1/PIGGY on the local bus CS1
114 #define CONFIG_SYS_NS16550_SERIAL
115 #define CONFIG_SYS_NS16550_REG_SIZE 1
116 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
118 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
119 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
122 * QE UEC ethernet configuration
124 #define CONFIG_UEC_ETH
125 #define CONFIG_ETHPRIME "UEC0"
127 #define CONFIG_UEC_ETH1 /* GETH1 */
128 #define UEC_VERBOSE_DEBUG 1
130 #ifdef CONFIG_UEC_ETH1
131 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
132 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
133 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
134 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
135 #define CONFIG_SYS_UEC1_PHY_ADDR 0
136 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
137 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
144 #ifndef CONFIG_SYS_RAMBOOT
145 #ifndef CONFIG_ENV_ADDR
146 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
147 CONFIG_SYS_MONITOR_LEN)
149 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
150 #ifndef CONFIG_ENV_OFFSET
151 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
154 /* Address and size of Redundant Environment Sector */
155 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
156 CONFIG_ENV_SECT_SIZE)
157 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
159 #else /* CFG_SYS_RAMBOOT */
160 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
161 #define CONFIG_ENV_SIZE 0x2000
162 #endif /* CFG_SYS_RAMBOOT */
165 #define CONFIG_SYS_I2C
166 #define CONFIG_SYS_NUM_I2C_BUSES 4
167 #define CONFIG_SYS_I2C_MAX_HOPS 1
168 #define CONFIG_SYS_I2C_FSL
169 #define CONFIG_SYS_FSL_I2C_SPEED 200000
170 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
171 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
172 #define CONFIG_SYS_I2C_OFFSET 0x3000
173 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
174 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
175 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
176 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
177 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
178 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
179 {1, {I2C_NULL_HOP} } }
181 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
183 #if defined(CONFIG_CMD_NAND)
184 #define CONFIG_NAND_KMETER1
185 #define CONFIG_SYS_MAX_NAND_DEVICE 1
186 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
190 * For booting Linux, the board info and command line data
191 * have to be in the first 8 MB of memory, since this is
192 * the maximum mapped by the Linux kernel during initialization.
194 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
197 * Internal Definitions
199 #define BOOTFLASH_START 0xF0000000
201 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
204 * Environment Configuration
206 #define CONFIG_ENV_OVERWRITE
207 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
208 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
211 #ifndef CONFIG_KM_DEF_ARCH
212 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
215 #define CONFIG_EXTRA_ENV_SETTINGS \
219 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
220 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
224 #if defined(CONFIG_UEC_ETH)
225 #define CONFIG_HAS_ETH0
231 #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
233 #define CONFIG_SYS_DDRCDR (\
239 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
240 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
245 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
246 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
247 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
248 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
250 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
251 CSCONFIG_ODT_WR_CFG | \
252 CSCONFIG_ROW_BIT_13 | \
255 #define CONFIG_SYS_DDR_MODE 0x47860242
256 #define CONFIG_SYS_DDR_MODE2 0x8080c000
258 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
259 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
260 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
261 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
262 (0 << TIMING_CFG0_WWT_SHIFT) | \
263 (0 << TIMING_CFG0_RRT_SHIFT) | \
264 (0 << TIMING_CFG0_WRT_SHIFT) | \
265 (0 << TIMING_CFG0_RWT_SHIFT))
267 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
268 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
269 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
270 (3 << TIMING_CFG1_WRREC_SHIFT) | \
271 (7 << TIMING_CFG1_REFREC_SHIFT) | \
272 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
273 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
274 (3 << TIMING_CFG1_PRETOACT_SHIFT))
276 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
277 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
278 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
279 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
280 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
281 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
282 (5 << TIMING_CFG2_CPO_SHIFT))
284 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
286 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
287 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
290 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
293 * Init Local Bus Memory Controller:
295 * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2
296 * -----------------------------------------------------------------------------
297 * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE
298 * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit)
300 * Device on board (continued)
301 * Bank Bus Machine PortSz Size KMTEPR2
302 * -----------------------------------------------------------------------------
303 * 2 Local GPCM 8 bit 256MB NVRAM
304 * 3 Local GPCM 8 bit 256MB TEP2 (16 bit)
308 #endif /* __CONFIG_H */