include/configs/tuda1.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * (C) Copyright 2008
  12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13  *
  14  * (C) Copyright 2010-2011
  15  * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation; either version 2 of
  20  * the License, or (at your option) any later version.
  21  */
  22
  23 #ifndef __CONFIG_H
  24 #define __CONFIG_H
  25
  26 /*
  27  * High Level Configuration Options
  28  */
  29 #define CONFIG_TUDA1            /* TUDA1 board specific */
  30 #define CONFIG_HOSTNAME         tuda1
  31 #define CONFIG_KM_BOARD_NAME   "tuda1"
  32
  33 #define CONFIG_SYS_TEXT_BASE    0xF0000000
  34
  35 /* include common defines/options for all 8321 Keymile boards */
  36 #include "km/km8321-common.h"
  37
  38 #define CONFIG_SYS_APP1_BASE    0xA0000000    /* PAXG */
  39 #define CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
  40 #define CONFIG_SYS_APP2_BASE    0xB0000000    /* PINC3 */
  41 #define CONFIG_SYS_APP2_SIZE    256 /* Megabytes */
  42
  43 /*
  44  * Local Bus Configuration & Clock Setup
  45  */
  46 #define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
  47 #define CONFIG_SYS_LBC_LBCR     0x00000000
  48
  49 /*
  50  * Init Local Bus Memory Controller:
  51  *
  52  * Bank Bus     Machine PortSz  Size  Device
  53  * ---- ---     ------- ------  -----  ------
  54  *  2   Local   GPCM    8 bit  256MB    PAXG
  55  *  3   Local   GPCM    8 bit  256MB    PINC3
  56  *
  57  */
  58
  59 /*
  60  * PAXG on the local bus CS2
  61  */
  62 /* Window base at flash base */
  63 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
  64 /* Window size: 256 MB */
  65 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
  66
  67 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
  68                                  BR_PS_8 | \
  69                                  BR_MS_GPCM | \
  70                                  BR_V)
  71
  72 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
  73                                  OR_GPCM_CSNT | \
  74                                  OR_GPCM_ACS_DIV4 | \
  75                                  OR_GPCM_SCY_2 | \
  76                                  OR_GPCM_TRLX_SET | \
  77                                  OR_GPCM_EHTR_CLEAR | \
  78                                  OR_GPCM_EAD)
  79 /*
  80  * PINC3 on the local bus CS3
  81  */
  82 /* Access window base at PINC3 base */
  83 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
  84 /* Window size: 256 MB */
  85 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
  86
  87 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
  88                                  BR_PS_8 |              \
  89                                  BR_MS_GPCM |           \
  90                                  BR_V)
  91
  92 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
  93                                  OR_GPCM_CSNT | \
  94                                  OR_GPCM_ACS_DIV2 | \
  95                                  OR_GPCM_SCY_2 | \
  96                                  OR_GPCM_TRLX_SET | \
  97                                  OR_GPCM_EHTR_CLEAR)
  98
  99 #define CONFIG_SYS_MAMR         (MxMR_GPL_x4DIS | \
 100                                  0x0000c000 | \
 101                                  MxMR_WLFx_2X)
 102
 103 /*
 104  * MMU Setup
 105  */
 106 /* PAXG:  icache cacheable, but dcache-inhibit and guarded */
 107 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | \
 108                                  BATL_PP_RW | \
 109                                  BATL_MEMCOHERENCE)
 110 /* 512M should also include APP2... */
 111 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | \
 112                                  BATU_BL_256M | \
 113                                  BATU_VS | \
 114                                  BATU_VP)
 115 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | \
 116                                  BATL_PP_RW | \
 117                                  BATL_CACHEINHIBIT | \
 118                                  BATL_GUARDEDSTORAGE)
 119 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 120
 121 /* PINC3:  icache cacheable, but dcache-inhibit and guarded */
 122 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | \
 123                                  BATL_PP_RW | \
 124                                  BATL_MEMCOHERENCE)
 125 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | \
 126                                  BATU_BL_256M | \
 127                                  BATU_VS | \
 128                                  BATU_VP)
 129 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | \
 130                                  BATL_PP_RW | \
 131                                  BATL_CACHEINHIBIT | \
 132                                  BATL_GUARDEDSTORAGE)
 133 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 134
 135 #define CONFIG_SYS_IBAT7L       (0)
 136 #define CONFIG_SYS_IBAT7U       (0)
 137 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 138 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 139
 140 #endif /* __CONFIG_H */