2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
14 * (C) Copyright 2010-2011
15 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
27 * High Level Configuration Options
29 #define CONFIG_TUDA1 /* TUDA1 board specific */
30 #define CONFIG_HOSTNAME tuda1
31 #define CONFIG_KM_BOARD_NAME "tuda1"
33 #define CONFIG_SYS_TEXT_BASE 0xF0000000
35 /* include common defines/options for all 8321 Keymile boards */
36 #include "km/km8321-common.h"
38 #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
39 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
40 #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
41 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
44 * Local Bus Configuration & Clock Setup
46 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
47 #define CONFIG_SYS_LBC_LBCR 0x00000000
50 * Init Local Bus Memory Controller:
52 * Bank Bus Machine PortSz Size Device
53 * ---- --- ------- ------ ----- ------
54 * 2 Local GPCM 8 bit 256MB PAXG
55 * 3 Local GPCM 8 bit 256MB PINC3
60 * PAXG on the local bus CS2
62 /* Window base at flash base */
63 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
64 /* Window size: 256 MB */
65 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
67 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
72 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
77 (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
80 * PINC3 on the local bus CS3
82 /* Access window base at PINC3 base */
83 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
84 /* Window size: 256 MB */
85 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
87 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
92 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
94 (OR_GPCM_ACS_DIV2 & /* ACS = 11 */\
95 (~OR_GPCM_XACS)) | /* XACS = 0 */\
97 (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
100 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
107 /* PAXG: icache cacheable, but dcache-inhibit and guarded */
108 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \
111 /* 512M should also include APP2... */
112 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \
116 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \
118 BATL_CACHEINHIBIT | \
120 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
122 /* PINC3: icache cacheable, but dcache-inhibit and guarded */
123 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \
126 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \
130 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \
132 BATL_CACHEINHIBIT | \
134 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
136 #define CONFIG_SYS_IBAT7L (0)
137 #define CONFIG_SYS_IBAT7U (0)
138 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
139 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
141 #endif /* __CONFIG_H */