2 * Copyright (C) 2015, Savoir-faire Linux Inc.
4 * Derived from MX51EVK code by
5 * Guennadi Liakhovetski <lg@denx.de>
6 * Freescale Semiconductor, Inc.
8 * Configuration settings for the TS4800 Board
10 * SPDX-License-Identifier: GPL-2.0+
16 /* High Level Configuration Options */
19 #define CONFIG_SYS_NO_FLASH /* No NOR Flash */
20 #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */
22 #define CONFIG_HW_WATCHDOG
24 /* text base address used when linking */
25 #define CONFIG_SYS_TEXT_BASE 0x90008000
27 #include <asm/arch/imx-regs.h>
29 /* enable passing of ATAGs */
30 #define CONFIG_CMDLINE_TAG
31 #define CONFIG_SETUP_MEMORY_TAGS
32 #define CONFIG_INITRD_TAG
33 #define CONFIG_REVISION_TAG
36 * Size of malloc() pool
38 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
44 #define CONFIG_MXC_UART
45 #define CONFIG_MXC_UART_BASE UART1_BASE
46 #define CONFIG_MXC_GPIO
51 #define CONFIG_HARD_SPI /* puts SPI: ready */
52 #define CONFIG_MXC_SPI /* driver for the SPI controllers*/
57 #define CONFIG_FSL_ESDHC
58 #define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
60 #define CONFIG_GENERIC_MMC
67 #define CONFIG_PHY_SMSC
69 #define CONFIG_FEC_MXC
70 #define IMX_FEC_BASE FEC_BASE_ADDR
71 #define CONFIG_ETHPRIME "FEC"
72 #define CONFIG_FEC_MXC_PHYADDR 0
74 /* allow to overwrite serial and ethaddr */
75 #define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */
76 #define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */
77 #define CONFIG_BAUDRATE 115200
79 /***********************************************************
81 ***********************************************************/
83 /* Environment variables */
86 #define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */
88 #define CONFIG_EXTRA_ENV_SETTINGS \
91 "fdt_file=imx51-ts4800.dtb\0" \
92 "fdt_addr=0x90fe0000\0" \
95 "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
96 "mmcargs=setenv bootargs root=${mmcroot}\0" \
97 "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
99 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
100 "bootscript=echo Running bootscript from mmc ...; " \
102 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
103 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
104 "mmcboot=echo Booting from mmc ...; " \
105 "run mmcargs addtty; " \
106 "if run loadfdt; then " \
107 "bootz ${loadaddr} - ${fdt_addr}; " \
109 "echo ERR: cannot load FDT; " \
113 #define CONFIG_BOOTCOMMAND \
114 "mmc dev ${mmcdev}; if mmc rescan; then " \
115 "if run loadbootscript; then " \
118 "if run loadimage; then " \
125 * Miscellaneous configurable options
127 #define CONFIG_SYS_LONGHELP /* undef to save memory */
128 #define CONFIG_AUTO_COMPLETE
129 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
130 /* Print Buffer Size */
131 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
132 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
133 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
135 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
137 #define CONFIG_CMDLINE_EDITING
139 /*-----------------------------------------------------------------------
140 * Physical Memory Map
142 #define CONFIG_NR_DRAM_BANKS 1
143 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
144 #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
146 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
147 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
148 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
150 #define CONFIG_SYS_INIT_SP_OFFSET \
151 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
152 #define CONFIG_SYS_INIT_SP_ADDR \
153 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
156 #define CONFIG_SYS_DDR_CLKSEL 0
157 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
158 #define CONFIG_SYS_MAIN_PWR_ON
160 /*-----------------------------------------------------------------------
161 * Environment organization
164 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
165 #define CONFIG_ENV_SIZE (8 * 1024)
166 #define CONFIG_ENV_IS_IN_MMC
167 #define CONFIG_SYS_MMC_ENV_DEV 0