3 * Stefano Babic, DENX Gmbh, sbabic@denx.de
6 * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Marius Groeger <mgroeger@sysgo.de>
15 * Configuation settings for the LUBBOCK board.
17 * SPDX-License-Identifier: GPL-2.0+
24 * High Level Configuration Options
27 #define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */
30 #define CONFIG_BOARD_LATE_INIT
31 #define CONFIG_SYS_TEXT_BASE 0x0
33 /* we will never enable dcache, because we have to setup MMU first */
34 #define CONFIG_SYS_DCACHE_OFF
39 * Size of malloc() pool
41 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
48 * select serial console configuration
50 #define CONFIG_PXA_SERIAL
51 #define CONFIG_FFUART 1 /* we use FFUART on Conxs */
52 #define CONFIG_BTUART 1 /* we use BTUART on Conxs */
53 #define CONFIG_STUART 1 /* we use STUART on Conxs */
54 #define CONFIG_CONS_INDEX 3
56 /* allow to overwrite serial and ethaddr */
57 #define CONFIG_ENV_OVERWRITE
59 #define CONFIG_BAUDRATE 38400
61 #define CONFIG_DOS_PARTITION 1
64 * Command line configuration.
66 #include <config_cmd_default.h>
68 #define CONFIG_CMD_FAT
69 #define CONFIG_CMD_IMLS
70 #define CONFIG_CMD_PING
71 #define CONFIG_CMD_USB
73 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
75 #undef CONFIG_SHOW_BOOT_PROGRESS
77 #define CONFIG_BOOTDELAY 3
78 #define CONFIG_SERVERIP 192.168.1.99
79 #define CONFIG_BOOTCOMMAND "run boot_flash"
80 #define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
81 " rw root=/dev/ram initrd=0xa0800000,5m"
83 #define CONFIG_EXTRA_ENV_SETTINGS \
85 "mw.b 0xa0010000 0xff 0x20000; " \
87 "fatload mmc 0 0xa0010000 u-boot.bin; " \
89 "protect off 0x0 0x1ffff; " \
90 "erase 0x0 0x1ffff; " \
91 "cp.b 0xa0010000 0x0 0x20000; " \
93 "program_uzImage_mmc=" \
94 "mw.b 0xa0010000 0xff 0x180000; " \
96 "fatload mmc 0 0xa0010000 uzImage; " \
98 "protect off 0x40000 0x1bffff; " \
99 "erase 0x40000 0x1bffff; " \
100 "cp.b 0xa0010000 0x40000 0x180000; " \
102 "program_ramdisk_mmc=" \
103 "mw.b 0xa0010000 0xff 0x500000; " \
105 "fatload mmc 0 0xa0010000 ramdisk.gz; " \
107 "protect off 0x1c0000 0x6bffff; " \
108 "erase 0x1c0000 0x6bffff; " \
109 "cp.b 0xa0010000 0x1c0000 0x500000; " \
113 "fatload mmc 0 0xa0030000 uzImage && " \
114 "fatload mmc 0 0xa0800000 ramdisk.gz; " \
116 "bootm 0xa0030000; " \
119 "cp.b 0x1c0000 0xa0800000 0x500000; " \
122 #define CONFIG_SETUP_MEMORY_TAGS 1
123 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
124 /* #define CONFIG_INITRD_TAG 1 */
126 #if defined(CONFIG_CMD_KGDB)
127 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
131 * Miscellaneous configurable options
133 #define CONFIG_SYS_HUSH_PARSER 1
135 #define CONFIG_SYS_LONGHELP /* undef to save memory */
136 #ifdef CONFIG_SYS_HUSH_PARSER
137 #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
140 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
141 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
142 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
143 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
144 #define CONFIG_SYS_DEVICE_NULLDEV 1
146 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
147 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
149 #define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
151 #define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
154 #define CONFIG_GENERIC_MMC
155 #define CONFIG_PXA_MMC_GENERIC
156 #define CONFIG_CMD_MMC
157 #define CONFIG_SYS_MMC_BASE 0xF0000000
161 * Physical Memory Map
163 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
164 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
165 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
166 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
167 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
168 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
169 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
170 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
171 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
173 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
175 #define CONFIG_SYS_DRAM_BASE 0xa0000000
176 #define CONFIG_SYS_DRAM_SIZE 0x04000000
178 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
180 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
181 #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
186 #define CONFIG_SYS_GPSR0_VAL 0x00018000
187 #define CONFIG_SYS_GPSR1_VAL 0x00000000
188 #define CONFIG_SYS_GPSR2_VAL 0x400dc000
189 #define CONFIG_SYS_GPSR3_VAL 0x00000000
190 #define CONFIG_SYS_GPCR0_VAL 0x00000000
191 #define CONFIG_SYS_GPCR1_VAL 0x00000000
192 #define CONFIG_SYS_GPCR2_VAL 0x00000000
193 #define CONFIG_SYS_GPCR3_VAL 0x00000000
194 #define CONFIG_SYS_GPDR0_VAL 0x00018000
195 #define CONFIG_SYS_GPDR1_VAL 0x00028801
196 #define CONFIG_SYS_GPDR2_VAL 0x520dc000
197 #define CONFIG_SYS_GPDR3_VAL 0x0001E000
198 #define CONFIG_SYS_GAFR0_L_VAL 0x801c0000
199 #define CONFIG_SYS_GAFR0_U_VAL 0x00000013
200 #define CONFIG_SYS_GAFR1_L_VAL 0x6990100A
201 #define CONFIG_SYS_GAFR1_U_VAL 0x00000008
202 #define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
203 #define CONFIG_SYS_GAFR2_U_VAL 0x010900F2
204 #define CONFIG_SYS_GAFR3_L_VAL 0x54000003
205 #define CONFIG_SYS_GAFR3_U_VAL 0x00002401
206 #define CONFIG_SYS_GRER0_VAL 0x00000000
207 #define CONFIG_SYS_GRER1_VAL 0x00000000
208 #define CONFIG_SYS_GRER2_VAL 0x00000000
209 #define CONFIG_SYS_GRER3_VAL 0x00000000
211 #define CONFIG_SYS_GFER1_VAL 0x00000000
212 #define CONFIG_SYS_GFER3_VAL 0x00000020
215 #define CONFIG_SYS_GFER0_VAL 0x00000001
216 #define CONFIG_SYS_GFER2_VAL 0x00200000
218 #define CONFIG_SYS_GFER0_VAL 0x00000000
219 #define CONFIG_SYS_GFER2_VAL 0x00000000
222 #define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */
227 #define CONFIG_SYS_CKEN 0x01FFFFFF /* CHECK */
228 #define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */
234 #define CONFIG_SYS_MSC0_VAL 0x4df84df0
235 #define CONFIG_SYS_MSC1_VAL 0x7ff87ff4
237 #define CONFIG_SYS_MSC2_VAL 0xa2697ff8
239 #define CONFIG_SYS_MSC2_VAL 0xa26936d4
241 #define CONFIG_SYS_MDCNFG_VAL 0x880009C9
242 #define CONFIG_SYS_MDREFR_VAL 0x20ca201e
243 #define CONFIG_SYS_MDMRS_VAL 0x00220022
245 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000
246 #define CONFIG_SYS_SXCNFG_VAL 0x40044004
249 * PCMCIA and CF Interfaces
251 #define CONFIG_SYS_MECR_VAL 0x00000001
252 #define CONFIG_SYS_MCMEM0_VAL 0x00004204
253 #define CONFIG_SYS_MCMEM1_VAL 0x00010204
254 #define CONFIG_SYS_MCATT0_VAL 0x00010504
255 #define CONFIG_SYS_MCATT1_VAL 0x00010504
256 #define CONFIG_SYS_MCIO0_VAL 0x00008407
257 #define CONFIG_SYS_MCIO1_VAL 0x0000c108
259 #define CONFIG_DRIVER_DM9000 1
262 #define CONFIG_DM9000_BASE 0x0C800000
264 #define CONFIG_DM9000_BASE 0x08000000
267 #define DM9000_IO CONFIG_DM9000_BASE
268 #define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
270 #define CONFIG_USB_OHCI_NEW 1
271 #define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
272 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
273 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
274 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "trizepsiv"
275 #define CONFIG_USB_STORAGE 1
276 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
279 * FLASH and environment organization
282 #define CONFIG_SYS_FLASH_CFI
283 #define CONFIG_FLASH_CFI_DRIVER 1
285 #define CONFIG_SYS_MONITOR_BASE 0
286 #define CONFIG_SYS_MONITOR_LEN 0x40000
288 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
289 #define CONFIG_SYS_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
291 /* timeout values are in ticks */
292 #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
293 #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
295 /* write flash less slowly */
296 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
298 /* Unlock to be used with Intel chips */
299 #define CONFIG_SYS_FLASH_PROTECTION 1
301 /* Flash environment locations */
302 #define CONFIG_ENV_IS_IN_FLASH 1
303 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */
304 #define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */
305 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
307 /* Address and size of Redundant Environment Sector */
308 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
309 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
311 #endif /* __CONFIG_H */