2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Corscience GmbH & Co. KG
9 * Thomas Weber <weber@corscience.de>
11 * Configuration settings for the Tricorder board.
13 * SPDX-License-Identifier: GPL-2.0+
19 /* High Level Configuration Options */
20 #define CONFIG_SYS_THUMB_BUILD
21 #define CONFIG_OMAP /* in a TI OMAP core */
23 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
25 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
26 * 64 bytes before this address should be set aside for u-boot.img's
27 * header. That is 0x800FFFC0--0x80100000 should not be used for any
30 #define CONFIG_SYS_TEXT_BASE 0x80100000
32 #define CONFIG_SDRC /* The chip has SDRC controller */
34 #include <asm/arch/cpu.h> /* get chip and board defs */
35 #include <asm/arch/omap.h>
38 #define V_OSCK 26000000 /* Clock output from T2 */
39 #define V_SCLK (V_OSCK >> 1)
41 #define CONFIG_MISC_INIT_R
43 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
44 #define CONFIG_SETUP_MEMORY_TAGS
45 #define CONFIG_INITRD_TAG
46 #define CONFIG_REVISION_TAG
48 /* Size of malloc() pool */
49 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
51 /* Hardware drivers */
54 #define CONFIG_OMAP_GPIO
57 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */
61 /* NS16550 Configuration */
62 #define CONFIG_SYS_NS16550_SERIAL
63 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
64 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
66 /* select serial console configuration */
67 #define CONFIG_CONS_INDEX 3
68 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
69 #define CONFIG_SERIAL3 3
70 #define CONFIG_BAUDRATE 115200
71 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
75 #define CONFIG_SYS_I2C
76 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
77 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
78 #define CONFIG_SYS_I2C_OMAP34XX
82 #define CONFIG_CMD_EEPROM
83 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
84 #define CONFIG_SYS_EEPROM_BUS_NUM 1
87 #define CONFIG_TWL4030_POWER
88 #define CONFIG_TWL4030_LED
91 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
92 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
93 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
96 "384k(u-boot-env1)," \
98 "384k(u-boot-env2)," \
103 #define CONFIG_NAND_OMAP_GPMC
104 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
106 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
107 /* to access nand at */
109 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
112 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
113 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
115 /* commands to include */
116 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
117 #define CONFIG_CMD_NAND /* NAND support */
118 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
119 #define CONFIG_CMD_UBIFS /* UBIFS commands */
120 #define CONFIG_LZO /* LZO is needed for UBIFS */
122 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */
125 #define CONFIG_RBTREE
126 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
127 #define CONFIG_MTD_PARTITIONS
129 /* Environment information (this is the common part) */
132 /* hang() the board on panic() */
133 #define CONFIG_PANIC_HANG
135 /* environment placement (for NAND), is different for FLASHCARD but does not
137 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
138 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
139 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
140 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
142 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
143 * value can not be used here! */
144 #define CONFIG_LOADADDR 0x82000000
146 #define CONFIG_COMMON_ENV_SETTINGS \
147 "console=ttyO2,115200n8\0" \
150 "defaultdisplay=lcd\0" \
151 "kernelopts=mtdoops.mtddev=3\0" \
152 "mtdparts=" MTDPARTS_DEFAULT "\0" \
153 "mtdids=" MTDIDS_DEFAULT "\0" \
155 "setenv bootargs console=${console} " \
158 "vt.global_cursor_default=0 " \
160 "omapdss.def_disp=${defaultdisplay}\0"
162 #define CONFIG_BOOTCOMMAND "run autoboot"
164 /* specific environment settings for different use cases
165 * FLASHCARD: used to run a rdimage from sdcard to program the device
166 * 'NORMAL': used to boot kernel from sdcard, nand, ...
168 * The main aim for the FLASHCARD skin is to have an embedded environment
169 * which will not be influenced by any data already on the device.
171 #ifdef CONFIG_FLASHCARD
173 #define CONFIG_ENV_IS_NOWHERE
175 /* the rdaddr is 16 MiB before the loadaddr */
176 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
178 #define CONFIG_EXTRA_ENV_SETTINGS \
179 CONFIG_COMMON_ENV_SETTINGS \
183 "setenv bootargs ${bootargs} " \
184 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
185 "rdinit=/sbin/init; " \
186 "mmc dev ${mmcdev}; mmc rescan; " \
187 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
188 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
189 "bootm ${loadaddr} ${rdaddr}\0"
191 #else /* CONFIG_FLASHCARD */
193 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
195 #define CONFIG_ENV_IS_IN_NAND
197 #define CONFIG_EXTRA_ENV_SETTINGS \
198 CONFIG_COMMON_ENV_SETTINGS \
201 "setenv bootargs ${bootargs} " \
202 "root=/dev/mmcblk0p2 " \
207 "setenv bootargs ${bootargs} " \
210 "rootfstype=ubifs " \
212 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
213 "bootscript=echo Running bootscript from mmc ...; " \
214 "source ${loadaddr}\0" \
215 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
216 "mmcboot=echo Booting from mmc ...; " \
218 "bootm ${loadaddr}\0" \
219 "loaduimage_ubi=ubi part ubi; " \
220 "ubifsmount ubi:root; " \
221 "ubifsload ${loadaddr} /boot/uImage\0" \
222 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
223 "nandboot=echo Booting from nand ...; " \
225 "run loaduimage_nand; " \
226 "bootm ${loadaddr}\0" \
227 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
228 "if run loadbootscript; then " \
231 "if run loaduimage; then " \
233 "else run nandboot; " \
236 "else run nandboot; fi\0"
238 #endif /* CONFIG_FLASHCARD */
240 /* Miscellaneous configurable options */
241 #define CONFIG_SYS_LONGHELP /* undef to save memory */
242 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */
243 #define CONFIG_AUTO_COMPLETE
244 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
245 /* Print Buffer Size */
246 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
247 sizeof(CONFIG_SYS_PROMPT) + 16)
248 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
250 /* Boot Argument Buffer Size */
251 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
253 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
254 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
255 0x07000000) /* 112 MB */
257 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
260 * OMAP3 has 12 GP timers, they can be driven by the system clock
261 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
262 * This rate is divided by a local divisor.
264 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
265 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
267 /* Physical Memory Map */
268 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
269 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
270 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
272 /* NAND and environment organization */
273 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
275 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
276 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
277 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
278 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
279 CONFIG_SYS_INIT_RAM_SIZE - \
280 GENERATED_GBL_DATA_SIZE)
283 #define CONFIG_SYS_SRAM_START 0x40200000
284 #define CONFIG_SYS_SRAM_SIZE 0x10000
286 /* Defines for SPL */
287 #define CONFIG_SPL_FRAMEWORK
288 #define CONFIG_SPL_NAND_SIMPLE
290 #define CONFIG_SPL_BOARD_INIT
291 #define CONFIG_SPL_NAND_BASE
292 #define CONFIG_SPL_NAND_DRIVERS
293 #define CONFIG_SPL_NAND_ECC
294 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
295 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
296 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
298 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
299 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
300 CONFIG_SPL_TEXT_BASE)
302 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
303 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
305 /* NAND boot config */
306 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
307 #define CONFIG_SYS_NAND_PAGE_COUNT 64
308 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
309 #define CONFIG_SYS_NAND_OOBSIZE 64
310 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
311 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
312 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
313 13, 14, 16, 17, 18, 19, 20, 21, 22, \
314 23, 24, 25, 26, 27, 28, 30, 31, 32, \
315 33, 34, 35, 36, 37, 38, 39, 40, 41, \
316 42, 44, 45, 46, 47, 48, 49, 50, 51, \
319 #define CONFIG_SYS_NAND_ECCSIZE 512
320 #define CONFIG_SYS_NAND_ECCBYTES 13
321 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
323 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
325 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
326 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
328 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
329 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
331 #define CONFIG_SYS_ALT_MEMTEST
332 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
333 #endif /* __CONFIG_H */