2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Corscience GmbH & Co. KG
9 * Thomas Weber <weber@corscience.de>
11 * Configuration settings for the Tricorder board.
13 * SPDX-License-Identifier: GPL-2.0+
19 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
21 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
22 * 64 bytes before this address should be set aside for u-boot.img's
23 * header. That is 0x800FFFC0--0x80100000 should not be used for any
27 #include <asm/arch/cpu.h> /* get chip and board defs */
28 #include <asm/arch/omap.h>
31 #define V_OSCK 26000000 /* Clock output from T2 */
32 #define V_SCLK (V_OSCK >> 1)
34 #define CONFIG_MISC_INIT_R
36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
37 #define CONFIG_SETUP_MEMORY_TAGS
38 #define CONFIG_INITRD_TAG
39 #define CONFIG_REVISION_TAG
41 /* Size of malloc() pool */
42 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
44 /* Hardware drivers */
46 /* NS16550 Configuration */
47 #define CONFIG_SYS_NS16550_SERIAL
48 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
49 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
51 /* select serial console configuration */
52 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
53 #define CONFIG_SERIAL3 3
54 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
58 #define CONFIG_SYS_I2C
62 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
63 #define CONFIG_SYS_EEPROM_BUS_NUM 1
66 #define CONFIG_TWL4030_LED
69 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
71 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
73 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
74 /* to access nand at */
76 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
78 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
79 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
82 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
83 #define CONFIG_MTD_PARTITIONS
85 /* Environment information (this is the common part) */
88 /* hang() the board on panic() */
90 /* environment placement (for NAND), is different for FLASHCARD but does not
92 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
93 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
94 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
95 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
97 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
98 * value can not be used here! */
99 #define CONFIG_LOADADDR 0x82000000
101 #define CONFIG_COMMON_ENV_SETTINGS \
102 "console=ttyO2,115200n8\0" \
105 "defaultdisplay=lcd\0" \
106 "kernelopts=mtdoops.mtddev=3\0" \
107 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
108 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
110 "setenv bootargs console=${console} " \
113 "vt.global_cursor_default=0 " \
115 "omapdss.def_disp=${defaultdisplay}\0"
117 #define CONFIG_BOOTCOMMAND "run autoboot"
119 /* specific environment settings for different use cases
120 * FLASHCARD: used to run a rdimage from sdcard to program the device
121 * 'NORMAL': used to boot kernel from sdcard, nand, ...
123 * The main aim for the FLASHCARD skin is to have an embedded environment
124 * which will not be influenced by any data already on the device.
126 #ifdef CONFIG_FLASHCARD
127 /* the rdaddr is 16 MiB before the loadaddr */
128 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
130 #define CONFIG_EXTRA_ENV_SETTINGS \
131 CONFIG_COMMON_ENV_SETTINGS \
135 "setenv bootargs ${bootargs} " \
136 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
137 "rdinit=/sbin/init; " \
138 "mmc dev ${mmcdev}; mmc rescan; " \
139 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
140 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
141 "bootm ${loadaddr} ${rdaddr}\0"
143 #else /* CONFIG_FLASHCARD */
145 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
147 #define CONFIG_EXTRA_ENV_SETTINGS \
148 CONFIG_COMMON_ENV_SETTINGS \
151 "setenv bootargs ${bootargs} " \
152 "root=/dev/mmcblk0p2 " \
157 "setenv bootargs ${bootargs} " \
160 "rootfstype=ubifs " \
162 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
163 "bootscript=echo Running bootscript from mmc ...; " \
164 "source ${loadaddr}\0" \
165 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
166 "mmcboot=echo Booting from mmc ...; " \
168 "bootm ${loadaddr}\0" \
169 "loaduimage_ubi=ubi part ubi; " \
170 "ubifsmount ubi:root; " \
171 "ubifsload ${loadaddr} /boot/uImage\0" \
172 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
173 "nandboot=echo Booting from nand ...; " \
175 "run loaduimage_nand; " \
176 "bootm ${loadaddr}\0" \
177 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
178 "if run loadbootscript; then " \
181 "if run loaduimage; then " \
183 "else run nandboot; " \
186 "else run nandboot; fi\0"
188 #endif /* CONFIG_FLASHCARD */
190 /* Miscellaneous configurable options */
191 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
193 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
194 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
195 0x07000000) /* 112 MB */
197 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
200 * OMAP3 has 12 GP timers, they can be driven by the system clock
201 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
202 * This rate is divided by a local divisor.
204 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
205 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
207 /* Physical Memory Map */
208 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
209 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
210 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
212 /* NAND and environment organization */
213 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
215 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
216 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
217 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
218 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
219 CONFIG_SYS_INIT_RAM_SIZE - \
220 GENERATED_GBL_DATA_SIZE)
223 #define CONFIG_SYS_SRAM_START 0x40200000
224 #define CONFIG_SYS_SRAM_SIZE 0x10000
226 /* Defines for SPL */
228 #define CONFIG_SPL_NAND_BASE
229 #define CONFIG_SPL_NAND_DRIVERS
230 #define CONFIG_SPL_NAND_ECC
231 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
232 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
234 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
235 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
236 CONFIG_SPL_TEXT_BASE)
238 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
239 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
241 /* NAND boot config */
242 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
243 #define CONFIG_SYS_NAND_PAGE_COUNT 64
244 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
245 #define CONFIG_SYS_NAND_OOBSIZE 64
246 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
247 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
248 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
249 13, 14, 16, 17, 18, 19, 20, 21, 22, \
250 23, 24, 25, 26, 27, 28, 30, 31, 32, \
251 33, 34, 35, 36, 37, 38, 39, 40, 41, \
252 42, 44, 45, 46, 47, 48, 49, 50, 51, \
255 #define CONFIG_SYS_NAND_ECCSIZE 512
256 #define CONFIG_SYS_NAND_ECCBYTES 13
257 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
259 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
261 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
262 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
264 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
265 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
267 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
268 #endif /* __CONFIG_H */