2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Corscience GmbH & Co. KG
9 * Thomas Weber <weber@corscience.de>
11 * Configuration settings for the Tricorder board.
13 * SPDX-License-Identifier: GPL-2.0+
19 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
21 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
22 * 64 bytes before this address should be set aside for u-boot.img's
23 * header. That is 0x800FFFC0--0x80100000 should not be used for any
26 #define CONFIG_SYS_TEXT_BASE 0x80100000
28 #include <asm/arch/cpu.h> /* get chip and board defs */
29 #include <asm/arch/omap.h>
32 #define V_OSCK 26000000 /* Clock output from T2 */
33 #define V_SCLK (V_OSCK >> 1)
35 #define CONFIG_MISC_INIT_R
37 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
38 #define CONFIG_SETUP_MEMORY_TAGS
39 #define CONFIG_INITRD_TAG
40 #define CONFIG_REVISION_TAG
42 /* Size of malloc() pool */
43 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
45 /* Hardware drivers */
47 /* NS16550 Configuration */
48 #define CONFIG_SYS_NS16550_SERIAL
49 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
50 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
52 /* select serial console configuration */
53 #define CONFIG_CONS_INDEX 3
54 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
55 #define CONFIG_SERIAL3 3
56 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
60 #define CONFIG_SYS_I2C
61 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
62 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
66 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
67 #define CONFIG_SYS_EEPROM_BUS_NUM 1
70 #define CONFIG_TWL4030_LED
73 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
75 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
77 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
78 /* to access nand at */
80 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
82 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
83 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
86 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
87 #define CONFIG_MTD_PARTITIONS
89 /* Environment information (this is the common part) */
92 /* hang() the board on panic() */
94 /* environment placement (for NAND), is different for FLASHCARD but does not
96 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
97 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
98 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
99 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
101 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
102 * value can not be used here! */
103 #define CONFIG_LOADADDR 0x82000000
105 #define CONFIG_COMMON_ENV_SETTINGS \
106 "console=ttyO2,115200n8\0" \
109 "defaultdisplay=lcd\0" \
110 "kernelopts=mtdoops.mtddev=3\0" \
111 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
112 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
114 "setenv bootargs console=${console} " \
117 "vt.global_cursor_default=0 " \
119 "omapdss.def_disp=${defaultdisplay}\0"
121 #define CONFIG_BOOTCOMMAND "run autoboot"
123 /* specific environment settings for different use cases
124 * FLASHCARD: used to run a rdimage from sdcard to program the device
125 * 'NORMAL': used to boot kernel from sdcard, nand, ...
127 * The main aim for the FLASHCARD skin is to have an embedded environment
128 * which will not be influenced by any data already on the device.
130 #ifdef CONFIG_FLASHCARD
131 /* the rdaddr is 16 MiB before the loadaddr */
132 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
134 #define CONFIG_EXTRA_ENV_SETTINGS \
135 CONFIG_COMMON_ENV_SETTINGS \
139 "setenv bootargs ${bootargs} " \
140 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
141 "rdinit=/sbin/init; " \
142 "mmc dev ${mmcdev}; mmc rescan; " \
143 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
144 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
145 "bootm ${loadaddr} ${rdaddr}\0"
147 #else /* CONFIG_FLASHCARD */
149 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
151 #define CONFIG_EXTRA_ENV_SETTINGS \
152 CONFIG_COMMON_ENV_SETTINGS \
155 "setenv bootargs ${bootargs} " \
156 "root=/dev/mmcblk0p2 " \
161 "setenv bootargs ${bootargs} " \
164 "rootfstype=ubifs " \
166 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
167 "bootscript=echo Running bootscript from mmc ...; " \
168 "source ${loadaddr}\0" \
169 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
170 "mmcboot=echo Booting from mmc ...; " \
172 "bootm ${loadaddr}\0" \
173 "loaduimage_ubi=ubi part ubi; " \
174 "ubifsmount ubi:root; " \
175 "ubifsload ${loadaddr} /boot/uImage\0" \
176 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
177 "nandboot=echo Booting from nand ...; " \
179 "run loaduimage_nand; " \
180 "bootm ${loadaddr}\0" \
181 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
182 "if run loadbootscript; then " \
185 "if run loaduimage; then " \
187 "else run nandboot; " \
190 "else run nandboot; fi\0"
192 #endif /* CONFIG_FLASHCARD */
194 /* Miscellaneous configurable options */
195 #define CONFIG_SYS_LONGHELP /* undef to save memory */
196 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */
197 #define CONFIG_AUTO_COMPLETE
198 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
200 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
201 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
202 0x07000000) /* 112 MB */
204 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
207 * OMAP3 has 12 GP timers, they can be driven by the system clock
208 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
209 * This rate is divided by a local divisor.
211 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
212 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
214 /* Physical Memory Map */
215 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
216 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
217 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
219 /* NAND and environment organization */
220 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
222 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
223 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
224 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
225 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
226 CONFIG_SYS_INIT_RAM_SIZE - \
227 GENERATED_GBL_DATA_SIZE)
230 #define CONFIG_SYS_SRAM_START 0x40200000
231 #define CONFIG_SYS_SRAM_SIZE 0x10000
233 /* Defines for SPL */
234 #define CONFIG_SPL_FRAMEWORK
236 #define CONFIG_SPL_NAND_BASE
237 #define CONFIG_SPL_NAND_DRIVERS
238 #define CONFIG_SPL_NAND_ECC
239 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
240 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
242 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
243 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
244 CONFIG_SPL_TEXT_BASE)
246 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
247 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
249 /* NAND boot config */
250 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
251 #define CONFIG_SYS_NAND_PAGE_COUNT 64
252 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
253 #define CONFIG_SYS_NAND_OOBSIZE 64
254 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
255 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
256 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
257 13, 14, 16, 17, 18, 19, 20, 21, 22, \
258 23, 24, 25, 26, 27, 28, 30, 31, 32, \
259 33, 34, 35, 36, 37, 38, 39, 40, 41, \
260 42, 44, 45, 46, 47, 48, 49, 50, 51, \
263 #define CONFIG_SYS_NAND_ECCSIZE 512
264 #define CONFIG_SYS_NAND_ECCBYTES 13
265 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
267 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
269 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
270 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
272 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
273 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
275 #define CONFIG_SYS_ALT_MEMTEST
276 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
277 #endif /* __CONFIG_H */