2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Corscience GmbH & Co. KG
9 * Thomas Weber <weber@corscience.de>
11 * Configuration settings for the Tricorder board.
13 * SPDX-License-Identifier: GPL-2.0+
19 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
21 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
22 * 64 bytes before this address should be set aside for u-boot.img's
23 * header. That is 0x800FFFC0--0x80100000 should not be used for any
26 #define CONFIG_SYS_TEXT_BASE 0x80100000
28 #define CONFIG_SDRC /* The chip has SDRC controller */
30 #include <asm/arch/cpu.h> /* get chip and board defs */
31 #include <asm/arch/omap.h>
34 #define V_OSCK 26000000 /* Clock output from T2 */
35 #define V_SCLK (V_OSCK >> 1)
37 #define CONFIG_MISC_INIT_R
39 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
40 #define CONFIG_SETUP_MEMORY_TAGS
41 #define CONFIG_INITRD_TAG
42 #define CONFIG_REVISION_TAG
44 /* Size of malloc() pool */
45 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
47 /* Hardware drivers */
49 /* NS16550 Configuration */
50 #define CONFIG_SYS_NS16550_SERIAL
51 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
52 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
54 /* select serial console configuration */
55 #define CONFIG_CONS_INDEX 3
56 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
57 #define CONFIG_SERIAL3 3
58 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
62 #define CONFIG_SYS_I2C
63 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
64 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
68 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
69 #define CONFIG_SYS_EEPROM_BUS_NUM 1
72 #define CONFIG_TWL4030_LED
75 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
76 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
77 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
80 "384k(u-boot-env1)," \
82 "384k(u-boot-env2)," \
87 #define CONFIG_NAND_OMAP_GPMC
88 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
90 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
91 /* to access nand at */
93 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
95 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
96 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
99 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
100 #define CONFIG_MTD_PARTITIONS
102 /* Environment information (this is the common part) */
105 /* hang() the board on panic() */
106 #define CONFIG_PANIC_HANG
108 /* environment placement (for NAND), is different for FLASHCARD but does not
110 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
111 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
112 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
113 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
115 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
116 * value can not be used here! */
117 #define CONFIG_LOADADDR 0x82000000
119 #define CONFIG_COMMON_ENV_SETTINGS \
120 "console=ttyO2,115200n8\0" \
123 "defaultdisplay=lcd\0" \
124 "kernelopts=mtdoops.mtddev=3\0" \
125 "mtdparts=" MTDPARTS_DEFAULT "\0" \
126 "mtdids=" MTDIDS_DEFAULT "\0" \
128 "setenv bootargs console=${console} " \
131 "vt.global_cursor_default=0 " \
133 "omapdss.def_disp=${defaultdisplay}\0"
135 #define CONFIG_BOOTCOMMAND "run autoboot"
137 /* specific environment settings for different use cases
138 * FLASHCARD: used to run a rdimage from sdcard to program the device
139 * 'NORMAL': used to boot kernel from sdcard, nand, ...
141 * The main aim for the FLASHCARD skin is to have an embedded environment
142 * which will not be influenced by any data already on the device.
144 #ifdef CONFIG_FLASHCARD
145 /* the rdaddr is 16 MiB before the loadaddr */
146 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
148 #define CONFIG_EXTRA_ENV_SETTINGS \
149 CONFIG_COMMON_ENV_SETTINGS \
153 "setenv bootargs ${bootargs} " \
154 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
155 "rdinit=/sbin/init; " \
156 "mmc dev ${mmcdev}; mmc rescan; " \
157 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
158 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
159 "bootm ${loadaddr} ${rdaddr}\0"
161 #else /* CONFIG_FLASHCARD */
163 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
165 #define CONFIG_EXTRA_ENV_SETTINGS \
166 CONFIG_COMMON_ENV_SETTINGS \
169 "setenv bootargs ${bootargs} " \
170 "root=/dev/mmcblk0p2 " \
175 "setenv bootargs ${bootargs} " \
178 "rootfstype=ubifs " \
180 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
181 "bootscript=echo Running bootscript from mmc ...; " \
182 "source ${loadaddr}\0" \
183 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
184 "mmcboot=echo Booting from mmc ...; " \
186 "bootm ${loadaddr}\0" \
187 "loaduimage_ubi=ubi part ubi; " \
188 "ubifsmount ubi:root; " \
189 "ubifsload ${loadaddr} /boot/uImage\0" \
190 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
191 "nandboot=echo Booting from nand ...; " \
193 "run loaduimage_nand; " \
194 "bootm ${loadaddr}\0" \
195 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
196 "if run loadbootscript; then " \
199 "if run loaduimage; then " \
201 "else run nandboot; " \
204 "else run nandboot; fi\0"
206 #endif /* CONFIG_FLASHCARD */
208 /* Miscellaneous configurable options */
209 #define CONFIG_SYS_LONGHELP /* undef to save memory */
210 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */
211 #define CONFIG_AUTO_COMPLETE
212 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
214 /* Boot Argument Buffer Size */
215 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
217 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
218 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
219 0x07000000) /* 112 MB */
221 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
224 * OMAP3 has 12 GP timers, they can be driven by the system clock
225 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
226 * This rate is divided by a local divisor.
228 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
229 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
231 /* Physical Memory Map */
232 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
233 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
234 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
236 /* NAND and environment organization */
237 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
239 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
240 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
241 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
242 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
243 CONFIG_SYS_INIT_RAM_SIZE - \
244 GENERATED_GBL_DATA_SIZE)
247 #define CONFIG_SYS_SRAM_START 0x40200000
248 #define CONFIG_SYS_SRAM_SIZE 0x10000
250 /* Defines for SPL */
251 #define CONFIG_SPL_FRAMEWORK
252 #define CONFIG_SPL_NAND_SIMPLE
254 #define CONFIG_SPL_NAND_BASE
255 #define CONFIG_SPL_NAND_DRIVERS
256 #define CONFIG_SPL_NAND_ECC
257 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
258 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
260 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
261 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
262 CONFIG_SPL_TEXT_BASE)
264 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
265 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
267 /* NAND boot config */
268 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
269 #define CONFIG_SYS_NAND_PAGE_COUNT 64
270 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
271 #define CONFIG_SYS_NAND_OOBSIZE 64
272 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
273 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
274 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
275 13, 14, 16, 17, 18, 19, 20, 21, 22, \
276 23, 24, 25, 26, 27, 28, 30, 31, 32, \
277 33, 34, 35, 36, 37, 38, 39, 40, 41, \
278 42, 44, 45, 46, 47, 48, 49, 50, 51, \
281 #define CONFIG_SYS_NAND_ECCSIZE 512
282 #define CONFIG_SYS_NAND_ECCBYTES 13
283 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
285 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
287 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
288 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
290 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
291 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
293 #define CONFIG_SYS_ALT_MEMTEST
294 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
295 #endif /* __CONFIG_H */