2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Corscience GmbH & Co. KG
9 * Thomas Weber <weber@corscience.de>
11 * Configuration settings for the Tricorder board.
13 * SPDX-License-Identifier: GPL-2.0+
19 /* High Level Configuration Options */
20 #define CONFIG_SYS_THUMB_BUILD
21 #define CONFIG_OMAP /* in a TI OMAP core */
22 #define CONFIG_OMAP_COMMON
23 /* Common ARM Erratas */
24 #define CONFIG_ARM_ERRATA_454179
25 #define CONFIG_ARM_ERRATA_430973
26 #define CONFIG_ARM_ERRATA_621766
28 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
30 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
31 * 64 bytes before this address should be set aside for u-boot.img's
32 * header. That is 0x800FFFC0--0x80100000 should not be used for any
35 #define CONFIG_SYS_TEXT_BASE 0x80100000
37 #define CONFIG_SDRC /* The chip has SDRC controller */
39 #include <asm/arch/cpu.h> /* get chip and board defs */
40 #include <asm/arch/omap.h>
42 /* Display CPU and Board information */
43 #define CONFIG_DISPLAY_BOARDINFO
45 #define CONFIG_SILENT_CONSOLE
48 #define V_OSCK 26000000 /* Clock output from T2 */
49 #define V_SCLK (V_OSCK >> 1)
51 #define CONFIG_MISC_INIT_R
53 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
54 #define CONFIG_SETUP_MEMORY_TAGS
55 #define CONFIG_INITRD_TAG
56 #define CONFIG_REVISION_TAG
58 /* Size of malloc() pool */
59 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
61 /* Hardware drivers */
64 #define CONFIG_OMAP_GPIO
67 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */
70 #define CONFIG_STATUS_LED
71 #define CONFIG_BOARD_SPECIFIC_LED
72 #define CONFIG_CMD_LED /* LED command */
73 #define STATUS_LED_BIT (1 << 0)
74 #define STATUS_LED_STATE STATUS_LED_ON
75 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
76 #define STATUS_LED_BIT1 (1 << 1)
77 #define STATUS_LED_STATE1 STATUS_LED_ON
78 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
79 #define STATUS_LED_BIT2 (1 << 2)
80 #define STATUS_LED_STATE2 STATUS_LED_ON
81 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
83 /* NS16550 Configuration */
84 #define CONFIG_SYS_NS16550_SERIAL
85 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
86 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
88 /* select serial console configuration */
89 #define CONFIG_CONS_INDEX 3
90 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
91 #define CONFIG_SERIAL3 3
92 #define CONFIG_BAUDRATE 115200
93 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
97 #define CONFIG_GENERIC_MMC
99 #define CONFIG_OMAP_HSMMC
100 #define CONFIG_DOS_PARTITION
103 #define CONFIG_SYS_I2C
104 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
105 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
106 #define CONFIG_SYS_I2C_OMAP34XX
110 #define CONFIG_CMD_EEPROM
111 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
112 #define CONFIG_SYS_EEPROM_BUS_NUM 1
115 #define CONFIG_TWL4030_POWER
116 #define CONFIG_TWL4030_LED
118 /* Board NAND Info */
119 #define CONFIG_SYS_NO_FLASH /* no NOR flash */
120 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
121 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
122 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
125 "384k(u-boot-env1)," \
127 "384k(u-boot-env2)," \
132 #define CONFIG_NAND_OMAP_GPMC
133 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
135 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
136 /* to access nand at */
138 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
141 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
142 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
144 /* commands to include */
145 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
146 #define CONFIG_CMD_NAND /* NAND support */
147 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
148 #define CONFIG_CMD_UBIFS /* UBIFS commands */
149 #define CONFIG_LZO /* LZO is needed for UBIFS */
151 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */
154 #define CONFIG_RBTREE
155 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
156 #define CONFIG_MTD_PARTITIONS
158 /* Environment information (this is the common part) */
161 /* hang() the board on panic() */
162 #define CONFIG_PANIC_HANG
164 /* environment placement (for NAND), is different for FLASHCARD but does not
166 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
167 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
168 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
169 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
171 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
172 * value can not be used here! */
173 #define CONFIG_LOADADDR 0x82000000
175 #define CONFIG_COMMON_ENV_SETTINGS \
176 "console=ttyO2,115200n8\0" \
179 "defaultdisplay=lcd\0" \
180 "kernelopts=mtdoops.mtddev=3\0" \
181 "mtdparts=" MTDPARTS_DEFAULT "\0" \
182 "mtdids=" MTDIDS_DEFAULT "\0" \
184 "setenv bootargs console=${console} " \
187 "vt.global_cursor_default=0 " \
189 "omapdss.def_disp=${defaultdisplay}\0"
191 #define CONFIG_BOOTCOMMAND "run autoboot"
193 /* specific environment settings for different use cases
194 * FLASHCARD: used to run a rdimage from sdcard to program the device
195 * 'NORMAL': used to boot kernel from sdcard, nand, ...
197 * The main aim for the FLASHCARD skin is to have an embedded environment
198 * which will not be influenced by any data already on the device.
200 #ifdef CONFIG_FLASHCARD
202 #define CONFIG_ENV_IS_NOWHERE
204 /* the rdaddr is 16 MiB before the loadaddr */
205 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
207 #define CONFIG_EXTRA_ENV_SETTINGS \
208 CONFIG_COMMON_ENV_SETTINGS \
212 "setenv bootargs ${bootargs} " \
213 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
214 "rdinit=/sbin/init; " \
215 "mmc dev ${mmcdev}; mmc rescan; " \
216 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
217 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
218 "bootm ${loadaddr} ${rdaddr}\0"
220 #else /* CONFIG_FLASHCARD */
222 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
224 #define CONFIG_ENV_IS_IN_NAND
226 #define CONFIG_EXTRA_ENV_SETTINGS \
227 CONFIG_COMMON_ENV_SETTINGS \
230 "setenv bootargs ${bootargs} " \
231 "root=/dev/mmcblk0p2 " \
236 "setenv bootargs ${bootargs} " \
239 "rootfstype=ubifs " \
241 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
242 "bootscript=echo Running bootscript from mmc ...; " \
243 "source ${loadaddr}\0" \
244 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
245 "mmcboot=echo Booting from mmc ...; " \
247 "bootm ${loadaddr}\0" \
248 "loaduimage_ubi=ubi part ubi; " \
249 "ubifsmount ubi:root; " \
250 "ubifsload ${loadaddr} /boot/uImage\0" \
251 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
252 "nandboot=echo Booting from nand ...; " \
254 "run loaduimage_nand; " \
255 "bootm ${loadaddr}\0" \
256 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
257 "if run loadbootscript; then " \
260 "if run loaduimage; then " \
262 "else run nandboot; " \
265 "else run nandboot; fi\0"
267 #endif /* CONFIG_FLASHCARD */
269 /* Miscellaneous configurable options */
270 #define CONFIG_SYS_LONGHELP /* undef to save memory */
271 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */
272 #define CONFIG_AUTO_COMPLETE
273 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
274 /* Print Buffer Size */
275 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
276 sizeof(CONFIG_SYS_PROMPT) + 16)
277 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
279 /* Boot Argument Buffer Size */
280 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
282 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
283 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
284 0x07000000) /* 112 MB */
286 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
289 * OMAP3 has 12 GP timers, they can be driven by the system clock
290 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
291 * This rate is divided by a local divisor.
293 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
294 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
296 /* Physical Memory Map */
297 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
298 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
299 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
301 /* NAND and environment organization */
302 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
304 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
305 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
306 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
307 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
308 CONFIG_SYS_INIT_RAM_SIZE - \
309 GENERATED_GBL_DATA_SIZE)
312 #define CONFIG_SYS_SRAM_START 0x40200000
313 #define CONFIG_SYS_SRAM_SIZE 0x10000
315 /* Defines for SPL */
316 #define CONFIG_SPL_FRAMEWORK
317 #define CONFIG_SPL_NAND_SIMPLE
319 #define CONFIG_SPL_BOARD_INIT
320 #define CONFIG_SPL_NAND_BASE
321 #define CONFIG_SPL_NAND_DRIVERS
322 #define CONFIG_SPL_NAND_ECC
323 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
324 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
325 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
326 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
328 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
329 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
330 CONFIG_SPL_TEXT_BASE)
332 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
333 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
335 /* NAND boot config */
336 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
337 #define CONFIG_SYS_NAND_PAGE_COUNT 64
338 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
339 #define CONFIG_SYS_NAND_OOBSIZE 64
340 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
341 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
342 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
343 13, 14, 16, 17, 18, 19, 20, 21, 22, \
344 23, 24, 25, 26, 27, 28, 30, 31, 32, \
345 33, 34, 35, 36, 37, 38, 39, 40, 41, \
346 42, 44, 45, 46, 47, 48, 49, 50, 51, \
349 #define CONFIG_SYS_NAND_ECCSIZE 512
350 #define CONFIG_SYS_NAND_ECCBYTES 13
351 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
353 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
355 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
356 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
358 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
359 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
361 #define CONFIG_SYS_ALT_MEMTEST
362 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
363 #endif /* __CONFIG_H */