2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Corscience GmbH & Co. KG
9 * Thomas Weber <weber@corscience.de>
11 * Configuration settings for the Tricorder board.
13 * SPDX-License-Identifier: GPL-2.0+
19 /* High Level Configuration Options */
20 #define CONFIG_OMAP /* in a TI OMAP core */
21 #define CONFIG_OMAP_COMMON
23 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
25 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
26 * 64 bytes before this address should be set aside for u-boot.img's
27 * header. That is 0x800FFFC0--0x80100000 should not be used for any
30 #define CONFIG_SYS_TEXT_BASE 0x80100000
32 #define CONFIG_SDRC /* The chip has SDRC controller */
34 #include <asm/arch/cpu.h> /* get chip and board defs */
35 #include <asm/arch/omap3.h>
37 #define CONFIG_SYS_GENERIC_BOARD
39 /* Display CPU and Board information */
40 #define CONFIG_DISPLAY_CPUINFO
41 #define CONFIG_DISPLAY_BOARDINFO
43 #define CONFIG_SILENT_CONSOLE
44 #define CONFIG_ZERO_BOOTDELAY_CHECK
47 #define V_OSCK 26000000 /* Clock output from T2 */
48 #define V_SCLK (V_OSCK >> 1)
50 #define CONFIG_MISC_INIT_R
52 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
53 #define CONFIG_SETUP_MEMORY_TAGS
54 #define CONFIG_INITRD_TAG
55 #define CONFIG_REVISION_TAG
57 #define CONFIG_OF_LIBFDT
59 /* Size of malloc() pool */
60 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
62 /* Hardware drivers */
65 #define CONFIG_OMAP_GPIO
68 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */
71 #define CONFIG_STATUS_LED
72 #define CONFIG_BOARD_SPECIFIC_LED
73 #define CONFIG_CMD_LED /* LED command */
74 #define STATUS_LED_BIT (1 << 0)
75 #define STATUS_LED_STATE STATUS_LED_ON
76 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
77 #define STATUS_LED_BIT1 (1 << 1)
78 #define STATUS_LED_STATE1 STATUS_LED_ON
79 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
80 #define STATUS_LED_BIT2 (1 << 2)
81 #define STATUS_LED_STATE2 STATUS_LED_ON
82 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
84 /* NS16550 Configuration */
85 #define CONFIG_SYS_NS16550
86 #define CONFIG_SYS_NS16550_SERIAL
87 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
88 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
90 /* select serial console configuration */
91 #define CONFIG_CONS_INDEX 3
92 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
93 #define CONFIG_SERIAL3 3
94 #define CONFIG_BAUDRATE 115200
95 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
99 #define CONFIG_GENERIC_MMC
101 #define CONFIG_OMAP_HSMMC
102 #define CONFIG_DOS_PARTITION
105 #define CONFIG_SYS_I2C
106 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
107 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
108 #define CONFIG_SYS_I2C_OMAP34XX
112 #define CONFIG_SYS_I2C_MULTI_EEPROMS
113 #define CONFIG_CMD_EEPROM
114 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
115 #define CONFIG_SYS_EEPROM_BUS_NUM 1
118 #define CONFIG_TWL4030_POWER
119 #define CONFIG_TWL4030_LED
121 /* Board NAND Info */
122 #define CONFIG_SYS_NO_FLASH /* no NOR flash */
123 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
124 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
125 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
128 "384k(u-boot-env1)," \
130 "384k(u-boot-env2)," \
135 #define CONFIG_NAND_OMAP_GPMC
136 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
138 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
139 /* to access nand at */
141 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
144 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
145 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
147 /* commands to include */
148 #include <config_cmd_default.h>
150 #define CONFIG_CMD_EXT2 /* EXT2 Support */
151 #define CONFIG_CMD_FAT /* FAT support */
152 #define CONFIG_CMD_I2C /* I2C serial bus support */
153 #define CONFIG_CMD_MMC /* MMC support */
154 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
155 #define CONFIG_CMD_NAND /* NAND support */
156 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
157 #define CONFIG_CMD_UBI /* UBI commands */
158 #define CONFIG_CMD_UBIFS /* UBIFS commands */
159 #define CONFIG_LZO /* LZO is needed for UBIFS */
161 #undef CONFIG_CMD_NET
162 #undef CONFIG_CMD_NFS
163 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
164 #undef CONFIG_CMD_IMI /* iminfo */
165 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */
168 #define CONFIG_RBTREE
169 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
170 #define CONFIG_MTD_PARTITIONS
172 /* Environment information (this is the common part) */
174 #define CONFIG_BOOTDELAY 0
176 /* hang() the board on panic() */
177 #define CONFIG_PANIC_HANG
179 /* environment placement (for NAND), is different for FLASHCARD but does not
181 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
182 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
183 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
184 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
186 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
187 * value can not be used here! */
188 #define CONFIG_LOADADDR 0x82000000
190 #define CONFIG_COMMON_ENV_SETTINGS \
191 "console=ttyO2,115200n8\0" \
194 "defaultdisplay=lcd\0" \
195 "kernelopts=mtdoops.mtddev=3\0" \
196 "mtdparts=" MTDPARTS_DEFAULT "\0" \
197 "mtdids=" MTDIDS_DEFAULT "\0" \
199 "setenv bootargs console=${console} " \
202 "vt.global_cursor_default=0 " \
204 "omapdss.def_disp=${defaultdisplay}\0"
206 #define CONFIG_BOOTCOMMAND "run autoboot"
208 /* specific environment settings for different use cases
209 * FLASHCARD: used to run a rdimage from sdcard to program the device
210 * 'NORMAL': used to boot kernel from sdcard, nand, ...
212 * The main aim for the FLASHCARD skin is to have an embedded environment
213 * which will not be influenced by any data already on the device.
215 #ifdef CONFIG_FLASHCARD
217 #define CONFIG_ENV_IS_NOWHERE
219 /* the rdaddr is 16 MiB before the loadaddr */
220 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
222 #define CONFIG_EXTRA_ENV_SETTINGS \
223 CONFIG_COMMON_ENV_SETTINGS \
227 "setenv bootargs ${bootargs} " \
228 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
229 "rdinit=/sbin/init; " \
230 "mmc dev ${mmcdev}; mmc rescan; " \
231 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
232 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
233 "bootm ${loadaddr} ${rdaddr}\0"
235 #else /* CONFIG_FLASHCARD */
237 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
239 #define CONFIG_ENV_IS_IN_NAND
241 #define CONFIG_EXTRA_ENV_SETTINGS \
242 CONFIG_COMMON_ENV_SETTINGS \
245 "setenv bootargs ${bootargs} " \
246 "root=/dev/mmcblk0p2 " \
251 "setenv bootargs ${bootargs} " \
254 "rootfstype=ubifs " \
256 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
257 "bootscript=echo Running bootscript from mmc ...; " \
258 "source ${loadaddr}\0" \
259 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
260 "mmcboot=echo Booting from mmc ...; " \
262 "bootm ${loadaddr}\0" \
263 "loaduimage_ubi=ubi part ubi; " \
264 "ubifsmount ubi:root; " \
265 "ubifsload ${loadaddr} /boot/uImage\0" \
266 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
267 "nandboot=echo Booting from nand ...; " \
269 "run loaduimage_nand; " \
270 "bootm ${loadaddr}\0" \
271 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
272 "if run loadbootscript; then " \
275 "if run loaduimage; then " \
277 "else run nandboot; " \
280 "else run nandboot; fi\0"
282 #endif /* CONFIG_FLASHCARD */
284 /* Miscellaneous configurable options */
285 #define CONFIG_SYS_LONGHELP /* undef to save memory */
286 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
287 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */
288 #define CONFIG_AUTO_COMPLETE
289 #define CONFIG_SYS_PROMPT "OMAP3 Tricorder # "
290 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
291 /* Print Buffer Size */
292 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
293 sizeof(CONFIG_SYS_PROMPT) + 16)
294 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
296 /* Boot Argument Buffer Size */
297 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
299 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
300 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
301 0x07000000) /* 112 MB */
303 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
306 * OMAP3 has 12 GP timers, they can be driven by the system clock
307 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
308 * This rate is divided by a local divisor.
310 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
311 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
313 /* Physical Memory Map */
314 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
315 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
316 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
318 /* NAND and environment organization */
319 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
321 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
322 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
323 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
324 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
325 CONFIG_SYS_INIT_RAM_SIZE - \
326 GENERATED_GBL_DATA_SIZE)
329 #define CONFIG_SYS_SRAM_START 0x40200000
330 #define CONFIG_SYS_SRAM_SIZE 0x10000
332 /* Defines for SPL */
333 #define CONFIG_SPL_FRAMEWORK
334 #define CONFIG_SPL_NAND_SIMPLE
336 #define CONFIG_SPL_BOARD_INIT
337 #define CONFIG_SPL_GPIO_SUPPORT
338 #define CONFIG_SPL_LIBCOMMON_SUPPORT
339 #define CONFIG_SPL_LIBDISK_SUPPORT
340 #define CONFIG_SPL_I2C_SUPPORT
341 #define CONFIG_SPL_LIBGENERIC_SUPPORT
342 #define CONFIG_SPL_SERIAL_SUPPORT
343 #define CONFIG_SPL_POWER_SUPPORT
344 #define CONFIG_SPL_NAND_SUPPORT
345 #define CONFIG_SPL_NAND_BASE
346 #define CONFIG_SPL_NAND_DRIVERS
347 #define CONFIG_SPL_NAND_ECC
348 #define CONFIG_SPL_MMC_SUPPORT
349 #define CONFIG_SPL_FAT_SUPPORT
350 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
351 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
352 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
353 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
355 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
356 #define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */
357 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
359 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
360 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
362 /* NAND boot config */
363 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
364 #define CONFIG_SYS_NAND_PAGE_COUNT 64
365 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
366 #define CONFIG_SYS_NAND_OOBSIZE 64
367 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
368 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
369 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
370 13, 14, 16, 17, 18, 19, 20, 21, 22, \
371 23, 24, 25, 26, 27, 28, 30, 31, 32, \
372 33, 34, 35, 36, 37, 38, 39, 40, 41, \
373 42, 44, 45, 46, 47, 48, 49, 50, 51, \
376 #define CONFIG_SYS_NAND_ECCSIZE 512
377 #define CONFIG_SYS_NAND_ECCBYTES 13
378 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
380 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
382 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
383 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
385 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
386 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
388 #define CONFIG_SYS_ALT_MEMTEST
389 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
390 #endif /* __CONFIG_H */