1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013 Samsung Electronics
4 * Sanghee Kim <sh0130.kim@samsung.com>
5 * Piotr Wilczek <p.wilczek@samsung.com>
7 * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board.
10 #ifndef __CONFIG_TRATS2_H
11 #define __CONFIG_TRATS2_H
13 #include <configs/exynos4-common.h>
15 #define CONFIG_TIZEN /* TIZEN lib */
17 #ifndef CONFIG_SYS_L2CACHE_OFF
18 #define CONFIG_SYS_L2_PL310
19 #define CONFIG_SYS_PL310_BASE 0x10502000
22 /* TRATS2 has 4 banks of DRAM */
23 #define CONFIG_SYS_SDRAM_BASE 0x40000000
24 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
25 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
27 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
28 - GENERATED_GBL_DATA_SIZE)
30 /* Tizen - partitions definitions */
31 #define PARTS_CSA "csa-mmc"
32 #define PARTS_BOOT "boot"
33 #define PARTS_QBOOT "qboot"
34 #define PARTS_CSC "csc"
35 #define PARTS_ROOT "platform"
36 #define PARTS_DATA "data"
37 #define PARTS_UMS "ums"
39 #define PARTS_DEFAULT \
40 "uuid_disk=${uuid_gpt_disk};" \
41 "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
42 "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
43 "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
44 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
45 "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
46 "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
47 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
49 #define CONFIG_DFU_ALT \
50 "u-boot raw 0x80 0x800;" \
52 "/modem.bin ext4 0 2;" \
53 "/exynos4412-trats2.dtb ext4 0 2;" \
54 ""PARTS_CSA" part 0 1;" \
55 ""PARTS_BOOT" part 0 2;" \
56 ""PARTS_QBOOT" part 0 3;" \
57 ""PARTS_CSC" part 0 4;" \
58 ""PARTS_ROOT" part 0 5;" \
59 ""PARTS_DATA" part 0 6;" \
60 ""PARTS_UMS" part 0 7;" \
61 "params.bin raw 0x38 0x8;" \
62 "/Image.itb ext4 0 2\0"
64 #define CONFIG_EXTRA_ENV_SETTINGS \
67 "if run loaddtb; then " \
68 "bootm 0x40007FC0 - ${fdtaddr};" \
70 "bootm 0x40007FC0;\0" \
72 "mmc dev 0 2; mmc write 0x51000000 0 0x800;" \
75 "mmc read 0x51000000 0x80 0x800; run updatebackup\0" \
77 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
78 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
80 "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
81 "boottrace=setenv opts initcall_debug; run bootcmd\0" \
84 "console=console=ttySAC2,115200n8\0" \
85 "kernelname=uImage\0" \
86 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
88 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
90 "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \
93 "opts=always_resume=1\0" \
94 "partitions=" PARTS_DEFAULT \
95 "dfu_alt_info=" CONFIG_DFU_ALT \
98 "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
99 "consoleoff=set console console=ram; save; reset\0" \
100 "spladdr=0x40000100\0" \
102 "splfile=falcon.bin\0" \
104 "setexpr spl_imgsize ${splsize} + 8 ;" \
105 "setenv spl_imgsize 0x${spl_imgsize};" \
106 "setexpr spl_imgaddr ${spladdr} - 8 ;" \
107 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
108 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
109 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
110 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
111 "spl export atags 0x40007FC0;" \
112 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
113 "mw.l ${spl_addr_tmp} ${splsize};" \
114 "ext4write mmc ${mmcdev}:${mmcbootpart}" \
115 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
116 "setenv spl_imgsize;" \
117 "setenv spl_imgaddr;" \
118 "setenv spl_addr_tmp;\0" \
120 "fdtaddr=40800000\0" \
124 /* Security subsystem - enable hw_rand() */
125 #define CONFIG_EXYNOS_ACE_SHA
127 /* Common misc for Samsung */
128 #define CONFIG_MISC_COMMON
130 /* Download menu - Samsung common */
131 #define CONFIG_LCD_MENU
133 /* Download menu - definitions for check keys */
136 #define KEY_PWR_PMIC_NAME "MAX77686_PMIC"
137 #define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1
138 #define KEY_PWR_STATUS_MASK (1 << 0)
139 #define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1
140 #define KEY_PWR_INTERRUPT_MASK (1 << 1)
142 #define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22
143 #define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33
144 #endif /* __ASSEMBLY__ */
147 #define LCD_BPP LCD_COLOR16
150 #define CONFIG_FB_ADDR 0x52504000
151 #define CONFIG_EXYNOS_MIPI_DSIM
152 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
154 #endif /* __CONFIG_H */