1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011 Samsung Electronics
4 * Heungjun Kim <riverful.kim@samsung.com>
6 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
9 #ifndef __CONFIG_TRATS_H
10 #define __CONFIG_TRATS_H
12 #include <configs/exynos4-common.h>
14 #ifndef CONFIG_SYS_L2CACHE_OFF
15 #define CONFIG_SYS_PL310_BASE 0x10502000
18 /* TRATS has 4 banks of DRAM */
19 #define CONFIG_SYS_SDRAM_BASE 0x40000000
20 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
21 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
23 /* Tizen - partitions definitions */
24 #define PARTS_CSA "csa-mmc"
25 #define PARTS_BOOT "boot"
26 #define PARTS_QBOOT "qboot"
27 #define PARTS_CSC "csc"
28 #define PARTS_ROOT "platform"
29 #define PARTS_DATA "data"
30 #define PARTS_UMS "ums"
32 #define PARTS_DEFAULT \
33 "uuid_disk=${uuid_gpt_disk};" \
34 "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
35 "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
36 "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
37 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
38 "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
39 "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
40 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
42 #define CONFIG_DFU_ALT \
43 "u-boot raw 0x80 0x400;" \
45 "/modem.bin ext4 0 2;" \
46 "/exynos4210-trats.dtb ext4 0 2;" \
47 ""PARTS_CSA" part 0 1;" \
48 ""PARTS_BOOT" part 0 2;" \
49 ""PARTS_QBOOT" part 0 3;" \
50 ""PARTS_CSC" part 0 4;" \
51 ""PARTS_ROOT" part 0 5;" \
52 ""PARTS_DATA" part 0 6;" \
53 ""PARTS_UMS" part 0 7;" \
54 "params.bin raw 0x38 0x8;" \
55 "/Image.itb ext4 0 2\0"
57 #define CONFIG_EXTRA_ENV_SETTINGS \
60 "if run loaddtb; then " \
61 "bootm 0x40007FC0 - ${fdtaddr};" \
63 "bootm 0x40007FC0;\0" \
65 "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
68 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
71 "setenv bootargs root=/dev/nfs rw " \
72 "nfsroot=${nfsroot},nolock,tcp " \
73 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
74 "${netmask}:generic:usb0:off ${console} ${meminfo}" \
77 "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
78 "${console} ${meminfo} " \
79 "initrd=0x43000000,8M ramdisk=8192\0" \
81 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
82 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
84 "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
85 "boottrace=setenv opts initcall_debug; run bootcmd\0" \
86 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
89 "console=console=ttySAC2,115200n8\0" \
90 "meminfo=crashkernel=32M@0x50000000\0" \
91 "nfsroot=/nfsroot/arm\0" \
93 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
94 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
99 "opts=always_resume=1\0" \
100 "partitions=" PARTS_DEFAULT \
101 "dfu_alt_info=" CONFIG_DFU_ALT \
102 "spladdr=0x40000100\0" \
104 "splfile=falcon.bin\0" \
106 "setexpr spl_imgsize ${splsize} + 8 ;" \
107 "setenv spl_imgsize 0x${spl_imgsize};" \
108 "setexpr spl_imgaddr ${spladdr} - 8 ;" \
109 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
110 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
111 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
112 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
113 "spl export atags 0x40007FC0;" \
114 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
115 "mw.l ${spl_addr_tmp} ${splsize};" \
116 "ext4write mmc ${mmcdev}:${mmcbootpart}" \
117 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
118 "setenv spl_imgsize;" \
119 "setenv spl_imgaddr;" \
120 "setenv spl_addr_tmp;\0" \
122 "fdtaddr=40800000\0" \
124 /* Falcon mode definitions */
128 /* Common misc for Samsung */
129 #define CONFIG_MISC_COMMON
131 /* Download menu - definitions for check keys */
134 #define KEY_PWR_PMIC_NAME "MAX8997_PMIC"
135 #define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1
136 #define KEY_PWR_STATUS_MASK (1 << 0)
137 #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1
138 #define KEY_PWR_INTERRUPT_MASK (1 << 0)
140 #define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20
141 #define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21
142 #endif /* __ASSEMBLY__ */
144 #endif /* __CONFIG_H */