1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011 Samsung Electronics
4 * Heungjun Kim <riverful.kim@samsung.com>
6 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
9 #ifndef __CONFIG_TRATS_H
10 #define __CONFIG_TRATS_H
12 #include <configs/exynos4-common.h>
16 #define CONFIG_TIZEN /* TIZEN lib */
18 #ifndef CONFIG_SYS_L2CACHE_OFF
19 #define CONFIG_SYS_L2_PL310
20 #define CONFIG_SYS_PL310_BASE 0x10502000
23 /* TRATS has 4 banks of DRAM */
24 #define CONFIG_SYS_SDRAM_BASE 0x40000000
25 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
26 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
28 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
29 - GENERATED_GBL_DATA_SIZE)
31 #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
33 #define CONFIG_SYS_MONITOR_BASE 0x00000000
35 /* Tizen - partitions definitions */
36 #define PARTS_CSA "csa-mmc"
37 #define PARTS_BOOT "boot"
38 #define PARTS_QBOOT "qboot"
39 #define PARTS_CSC "csc"
40 #define PARTS_ROOT "platform"
41 #define PARTS_DATA "data"
42 #define PARTS_UMS "ums"
44 #define PARTS_DEFAULT \
45 "uuid_disk=${uuid_gpt_disk};" \
46 "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
47 "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
48 "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
49 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
50 "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
51 "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
52 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
54 #define CONFIG_DFU_ALT \
55 "u-boot raw 0x80 0x400;" \
57 "/modem.bin ext4 0 2;" \
58 "/exynos4210-trats.dtb ext4 0 2;" \
59 ""PARTS_CSA" part 0 1;" \
60 ""PARTS_BOOT" part 0 2;" \
61 ""PARTS_QBOOT" part 0 3;" \
62 ""PARTS_CSC" part 0 4;" \
63 ""PARTS_ROOT" part 0 5;" \
64 ""PARTS_DATA" part 0 6;" \
65 ""PARTS_UMS" part 0 7;" \
66 "params.bin raw 0x38 0x8;" \
67 "/Image.itb ext4 0 2\0"
69 #define CONFIG_EXTRA_ENV_SETTINGS \
72 "if run loaddtb; then " \
73 "bootm 0x40007FC0 - ${fdtaddr};" \
75 "bootm 0x40007FC0;\0" \
77 "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
80 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
83 "setenv bootargs root=/dev/nfs rw " \
84 "nfsroot=${nfsroot},nolock,tcp " \
85 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
86 "${netmask}:generic:usb0:off ${console} ${meminfo}" \
89 "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
90 "${console} ${meminfo} " \
91 "initrd=0x43000000,8M ramdisk=8192\0" \
93 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
94 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
96 "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
97 "boottrace=setenv opts initcall_debug; run bootcmd\0" \
98 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
100 "rootfstype=ext4\0" \
101 "console=console=ttySAC2,115200n8\0" \
102 "meminfo=crashkernel=32M@0x50000000\0" \
103 "nfsroot=/nfsroot/arm\0" \
105 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
106 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
111 "opts=always_resume=1\0" \
112 "partitions=" PARTS_DEFAULT \
113 "dfu_alt_info=" CONFIG_DFU_ALT \
114 "spladdr=0x40000100\0" \
116 "splfile=falcon.bin\0" \
118 "setexpr spl_imgsize ${splsize} + 8 ;" \
119 "setenv spl_imgsize 0x${spl_imgsize};" \
120 "setexpr spl_imgaddr ${spladdr} - 8 ;" \
121 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
122 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
123 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
124 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
125 "spl export atags 0x40007FC0;" \
126 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
127 "mw.l ${spl_addr_tmp} ${splsize};" \
128 "ext4write mmc ${mmcdev}:${mmcbootpart}" \
129 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
130 "setenv spl_imgsize;" \
131 "setenv spl_imgaddr;" \
132 "setenv spl_addr_tmp;\0" \
134 "fdtaddr=40800000\0" \
136 /* Falcon mode definitions */
137 #define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100
141 /* Security subsystem - enable hw_rand() */
142 #define CONFIG_EXYNOS_ACE_SHA
144 /* Common misc for Samsung */
145 #define CONFIG_MISC_COMMON
147 /* Download menu - Samsung common */
148 #define CONFIG_LCD_MENU
150 /* Download menu - definitions for check keys */
153 #define KEY_PWR_PMIC_NAME "MAX8997_PMIC"
154 #define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1
155 #define KEY_PWR_STATUS_MASK (1 << 0)
156 #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1
157 #define KEY_PWR_INTERRUPT_MASK (1 << 0)
159 #define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20
160 #define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21
161 #endif /* __ASSEMBLY__ */
164 #define LCD_BPP LCD_COLOR16
167 #define CONFIG_FB_ADDR 0x52504000
168 #define CONFIG_EXYNOS_MIPI_DSIM
169 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
171 #endif /* __CONFIG_H */