2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 //#define CONFIG_SECURE_BOOT
27 //#define CONFIG_ROM_VERIFY_SPL
28 #define PRIMPUKPATH "/dev/block/mmcblk0boot0"
29 #define PRIMPUKSTART 512
30 #define PRIMPUKLEN 260
31 #define CONFIG_OF_LIBFDT
32 //#ifdef CONFIG_OF_LIBFDT
33 //MACH_TYPE_SC8830=2014
35 #define DT_PLATFROM_ID 8830
36 #define DT_HARDWARE_ID 0
38 #define DT_SLP_SOC_VER 0x20000
39 #define CONFIG_MULTI_DTS
41 //only used in fdl2 .in uart download, the debug infors from serial will break the download process.
42 #define CONFIG_FDL2_PRINT 0
43 #define BOOT_NATIVE_LINUX 1
44 #define BOOT_NATIVE_LINUX_MODEM 1
45 #define CONFIG_SILENT_CONSOLE
46 #define CONFIG_GPIOLIB 1
49 //#define CONFIG_SDRAMDISK
50 #define U_BOOT_SPRD_VER 1
51 /*#define SPRD_EVM_TAG_ON 1*/
52 #ifdef SPRD_EVM_TAG_ON
53 #define SPRD_EVM_ADDR_START 0x00026000
54 #define SPRD_EVM_TAG(_x) (*(((unsigned long *)SPRD_EVM_ADDR_START)+_x) = *(volatile unsigned long *)0x87003004)
56 #define CONFIG_L2_OFF 1
60 //#define CONFIG_YAFFS2 1
62 //#define BOOT_PART "boot"
63 #define BOOT_PART "kernel"
64 #define RECOVERY_PART "recovery"
65 #define UBIPAC_PART "ubipac"
68 * SPREADTRUM BIGPHONE board - SoC Configuration
70 //#define CONFIG_SP8830
72 #define CONFIG_SPX30G //tshark chip
73 #define CONFIG_SPX30G2 //tshark2 chip
75 #define CONFIG_TIZENZ3_3G
76 #define CONFIG_SP8830WCN
77 #define CONFIG_ADIE_SC2723S
79 #define CONFIG_SUPPORT_W
80 #define WDSP_ADR 0x88020000
81 #define WFIXNV_ADR 0x88240000
82 #define WRUNTIMENV_ADR 0x88280000
83 #define WMODEM_ADR 0x88300000
84 #define MODEM_ADR WMODEM_ADR
85 #define CONFIG_SUPPORT_WIFI
86 #define WCNMODEM_ADR 0x8a808000
87 #define WCNFIXNV_ADR 0x8a800000
88 #define WCNRUNTIMENV_ADR 0x8a820000
89 //#define WMODEM_CODE_COPY_ADR 0x50000000
90 //#define WCN_CODE_COPY_ADR 0x50003000
92 #define CP0_CODE_COPY_ADR 0x50000000
93 #define CP2_CODE_COPY_ADR 0x50003000
95 #define CONFIG_AUTODLOADER
97 #define CHIP_ENDIAN_LITTLE
98 #define _LITTLE_ENDIAN 1
102 #define CONFIG_EMMC_BOOT
105 #ifdef CONFIG_EMMC_BOOT
106 #define EMMC_SECTOR_SIZE 512
109 #define CONFIG_FS_EXT4
110 #define CONFIG_EXT4_WRITE
111 #define CONFIG_CMD_EXT4
112 #define CONFIG_CMD_EXT4_WRITE
114 //#define CONFIG_TIGER_MMC
115 #define CONFIG_EFI_PARTITION
116 //#define CONFIG_EMMC_SPL
117 #define CONFIG_SYS_EMMC_U_BOOT_SECTOR_NUM ((CONFIG_SYS_NAND_U_BOOT_SIZE+EMMC_SECTOR_SIZE-1)/EMMC_SECTOR_SIZE)
124 #define CONFIG_CMD_MMC
125 #ifdef CONFIG_CMD_MMC
126 #define CONFIG_CMD_FAT 1
127 #define CONFIG_FAT_WRITE 1
129 #define CONFIG_GENERIC_MMC 1
130 #define CONFIG_SDHCI 1
131 #define CONFIG_SDHCI_CTRL_NO_HISPD 1 /* disable high speed control */
132 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
133 #define CONFIG_MMC_SDMA 1
134 #define CONFIG_MV_SDHCI 1
135 #define CONFIG_DOS_PARTITION 1
136 #define CONFIG_EFI_PARTITION 1
137 #define CONFIG_SYS_MMC_NUM 1
138 #define CONFIG_SYS_MMC_BASE {0x20600000}
139 #define CONFIG_SYS_SD_BASE 0x20300000
142 #define BB_DRAM_TYPE_256MB_32BIT
144 #define CONFIG_SYS_HZ 1000
145 #define CONFIG_SPRD_TIMER_CLK 1000 /*32768*/
147 //#define CONFIG_SYS_HUSH_PARSER
149 #ifdef CONFIG_SYS_HUSH_PARSER
150 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
153 #define FIXNV_SIZE (2*128 * 1024)
154 #define PRODUCTINFO_SIZE (16 * 1024)
155 #define WMODEM_SIZE (0x800000)
156 #define WDSP_SIZE (0x200000)
157 #define WCNMODEM_SIZE (0x100000)
158 #define VMJALUNA_SIZE (0x64000) /* 400K */
159 #define RUNTIMENV_SIZE (3*128 * 1024)
160 #ifdef CONFIG_ROM_VERIFY_SPL
161 #define CONFIG_SPL_LOAD_LEN (0x8000) /* 32 KB */
162 #define CONFIG_BOOTINFO_LENGTH (0x200) /* 512 Bytes*/
163 #define PUBKEY_BSC_BLOCK_INDEX (CONFIG_SPL_LOAD_LEN - CONFIG_BOOTINFO_LENGTH * 2) / EMMC_SECTOR_SIZE
164 #define PUBKEY_VLR_BLOCK_INDEX 2
165 #define PUBKEY_READ_BLOCK_NUMS 1
166 #define CONFIG_SPL_HASH_LEN (0x400) /* 1KB */
168 #define CONFIG_SPL_LOAD_LEN (0x6000)
169 #define PUBKEY_BSC_BLOCK_INDEX 0
170 #define PUBKEY_VLR_BLOCK_INDEX 0
171 #define PUBKEY_READ_BLOCK_NUMS (SEC_HEADER_MAX_SIZE / EMMC_SECTOR_SIZE)
172 #define CONFIG_SPL_HASH_LEN (0xC00) /* 3KB */
175 #define PRODUCTINFO_ADR 0x80490000
177 /*#define CMDLINE_NEED_CONV */
179 #define WATCHDOG_LOAD_VALUE 0x4000
180 #define CONFIG_SYS_STACK_SIZE 0x400
181 //#define CONFIG_SYS_TEXT_BASZE 0x80f00000
183 //#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
185 /* NAND BOOT is the only boot method */
186 #define CONFIG_NAND_U_BOOT
187 #define DYNAMIC_CRC_TABLE
188 /* Start copying real U-boot from the second page */
189 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
190 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
191 #define RAM_TYPPE_IS_SDRAM 0
192 //#define FPGA_TRACE_DOWNLOAD //for download image from trace
194 /* Load U-Boot to this address */
195 #define CONFIG_SYS_NAND_U_BOOT_DST 0x9f600000
196 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
197 #define CONFIG_SYS_SDRAM_BASE 0x80000000
198 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + 256*1024*1024)
200 #ifdef CONFIG_NAND_SPL
201 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_END - 0x40000)
204 #define CONFIG_MMU_TABLE_ADDR (0x00020000)
205 #define CONFIG_SYS_INIT_SP_ADDR \
206 (CONFIG_SYS_SDRAM_END - 0x10000 - GENERATED_GBL_DATA_SIZE)
208 #define CONFIG_SKIP_LOWLEVEL_INIT
211 #define CONFIG_HW_WATCHDOG
212 //#define CONFIG_AUTOBOOT //used for FPGA test, auto boot other image
213 //#define CONFIG_DISPLAY_CPUINFO
215 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
216 #define CONFIG_SETUP_MEMORY_TAGS 1
217 #define CONFIG_INITRD_TAG 1
223 #define CONFIG_SYS_MALLOC_LEN (2 << 20) /* 1 MiB */
225 * Board has 2 32MB banks of DRAM but there is a bug when using
226 * both so only the first is configured
228 #define CONFIG_NR_DRAM_BANKS 1
230 #define PHYS_SDRAM_1 0x80000000
231 #define PHYS_SDRAM_1_SIZE 0x10000000
232 #if (CONFIG_NR_DRAM_BANKS == 2)
233 #define PHYS_SDRAM_2 0x90000000
234 #define PHYS_SDRAM_2_SIZE 0x10000000
237 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
238 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
239 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
244 #define CONFIG_SPRD_UART 1
245 #define CONFIG_SYS_SC8800X_UART1 1
246 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
247 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
248 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
249 #define CONFIG_SPRD_SPI
250 #define CONFIG_SPRD_I2C
251 #define CONFIG_SC8830_I2C
253 * Flash & Environment
255 /* No NOR flash present */
256 #define CONFIG_SYS_MONITOR_LEN ((CONFIG_SYS_NAND_U_BOOT_OFFS)+(CONFIG_SYS_NAND_U_BOOT_SIZE))
257 #define CONFIG_SYS_NO_FLASH 1
258 #define CONFIG_ENV_IS_NOWHERE
259 #define CONFIG_ENV_SIZE (128 * 1024)
261 #define CONFIG_ENV_IS_IN_NAND
262 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
263 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
267 #define CONFIG_CLK_PARA
269 #ifndef CONFIG_CLK_PARA
272 #define MAGIC_HEADER 0x5555AAAA
273 #define MAGIC_END 0xAAAA5555
274 #define CONFIG_PARA_VERSION 1
275 #define CLK_CA7_CORE ARM_CLK_1000M
276 #define CLK_CA7_AXI ARM_CLK_500M
277 #define CLK_CA7_DGB ARM_CLK_200M
278 #define CLK_CA7_AHB AHB_CLK_192M
279 #define CLK_CA7_APB APB_CLK_64M
280 #define CLK_PUB_AHB PUB_AHB_CLK_153_6M
281 #define CLK_AON_APB AON_APB_CLK_128M
282 #define DDR_FREQ 800000000
283 #define DCDC_ARM 1200
284 #define DCDC_CORE 1100
285 #define CONFIG_VOL_PARA
290 //#define CONFIG_NAND_SC8830
291 #define CONFIG_SPRD_NAND_REGS_BASE (0x20B00000)
292 #define CONFIG_SYS_MAX_NAND_DEVICE 1
293 #define CONFIG_SYS_NAND_BASE (0x20B00000)
294 //#define CONFIG_JFFS2_NAND
295 //#define CONFIG_SPRD_NAND_HWECC
296 #define CONFIG_SYS_NAND_HW_ECC
297 #define CONFIG_SYS_NAND_LARGEPAGE
298 //#define CONFIG_SYS_NAND_5_ADDR_CYCLE
300 #define CONFIG_SYS_64BIT_VSPRINTF
302 //#define CONFIG_CMD_MTDPARTS
303 //#define CONFIG_MTD_PARTITIONS
304 //#define CONFIG_MTD_DEVICE
305 //#define CONFIG_CMD_UBI
306 #define CONFIG_RBTREE
308 //#define CONFIG_CMD_UBIFS
310 //#ifdef CONFIG_CMD_UBIFS
311 //#define CONFIG_FS_UBIFS
314 /* U-Boot general configuration */
315 #define CONFIG_SYS_PROMPT "TM1 # " /* Monitor Command Prompt */
316 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
317 /* Print buffer sz */
318 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
319 sizeof(CONFIG_SYS_PROMPT) + 16)
320 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
321 /* Boot Argument Buffer Size */
322 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
323 #define CONFIG_CMDLINE_EDITING
324 #define CONFIG_SYS_LONGHELP
327 #define INFORM3 0xf90
329 /* support OS choose */
330 #undef CONFIG_BOOTM_NETBSD
331 #undef CONFIG_BOOTM_RTEMS
333 /* U-Boot commands */
334 #include <config_cmd_default.h>
335 //#define CONFIG_CMD_NAND
336 #undef CONFIG_CMD_FPGA
337 #undef CONFIG_CMD_LOADS
338 #undef CONFIG_CMD_NET
339 #undef CONFIG_CMD_NFS
340 #undef CONFIG_CMD_SETGETDCR
342 #define CONFIG_ENV_OVERWRITE
344 #ifdef SPRD_EVM_TAG_ON
345 #define CONFIG_BOOTDELAY 0
347 #define CONFIG_BOOTDELAY 0
348 #define CONFIG_ZERO_BOOTDELAY_CHECK
351 #define CONFIG_LOADADDR (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN - 4*1024*1024) /* loadaddr env var */
352 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
354 #define xstr(s) str(s)
357 #ifdef CONFIG_RAM_1G_512M
358 #define MEM_INIT_PARA "mem=1536M"
359 #elif defined(CONFIG_RAM1G)
360 #define MEM_INIT_PARA "mem=1024M"
361 #elif defined(CONFIG_RAM512M)
362 #define MEM_INIT_PARA "mem=512M"
363 #elif defined(CONFIG_RAM256M)
364 #define MEM_INIT_PARA "mem=256M"
365 //#elif defined(CONFIG_RAMxxxM)
366 ////#define MEM_INIT_PARA "mem=xxxM" //xxx maybe 1024 etc
368 #error "CONFIG_RAMxxxM macro must be defined"
370 #define MTDIDS_DEFAULT "nand0=sprd-nand"
371 //#define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),512k(2ndbl),256k(params),512k(vmjaluna),10m(modem),3840k(fixnv),3840k(backupfixnv),5120k(dsp),3840k(runtimenv),10m(boot),10m(recovery),250m(system),180m(userdata),20m(cache),256k(misc),1m(boot_logo),1m(fastboot_logo),3840k(productinfo),512k(kpanic)"
372 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),768k(2ndbl),512k(kpanic),-(ubipac)"
373 #define CONFIG_BOOTARGS MEM_INIT_PARA" loglevel=1 console=ttyS1,115200n8 init=/init " MTDPARTS_DEFAULT
376 #define CMDLINE_DEFAULT_TIZEN ""
378 #define CONFIG_FB_RAM_BASE 0x8fe2e000
379 #define SEC_LOG_LENGTH 0xffe00
380 #define CONFIG_BOOTLOADER_VER "tizen"
382 #define COPY_LINUX_KERNEL_SIZE (0x600000)
383 #define LINUX_INITRD_NAME "modem"
385 #define CONFIG_BOOTCOMMAND "cboot normal"
386 #define CONFIG_EXTRA_ENV_SETTINGS \
388 "muic_rustproof=0\0" \
392 "sec_log_addr=0x86b00000\0" \
393 "emmc_checksum=3\0" \
396 #define CONFIG_MMC_DEFAULT_DEV 1
398 /* Tizen - partitions definitions */
399 #define PARTS_BOOT "sboot"
400 #define PARTS_RECOVERY "recovery"
401 #define PARTS_KERNEL "kernel"
402 #define PARTS_MODULE "module"
403 #define PARTS_MODEM "modem"
404 #define PARTS_DSP "dsp"
405 #define PARTS_FIXNV1 "fixnv1"
406 #define PARTS_FIXNV2 "fixnv2"
407 #define PARTS_SYSDATA "system-data"
408 #define PARTS_USER "user"
409 #define PARTS_ROOTFS "rootfs"
410 #define PARTS_RUNTIMENV1 "runtimenv1"
411 #define PARTS_RUNTIMENV2 "runtimenv2"
412 #define PARTS_RAMDISK "ramdisk1"
413 #define PARTS_RAMDISK2 "ramdisk2"
415 #define CONFIG_RAMDISK_BOOT 1
419 #ifdef CONFIG_CMD_NET
420 #define CONFIG_IPADDR 192.168.10.2
421 #define CONFIG_SERVERIP 192.168.10.5
422 #define CONFIG_NETMASK 255.255.255.0
423 #define CONFIG_USBNET_DEVADDR 26:03:ee:00:87:9f
424 #define CONFIG_USBNET_HOSTADDR 9a:04:c7:d6:30:d0
426 #define CONFIG_NET_MULTI
427 #define CONFIG_CMD_DNS
428 #define CONFIG_CMD_NFS
429 #define CONFIG_CMD_RARP
430 #define CONFIG_CMD_PING
431 /*#define CONFIG_CMD_SNTP */
434 #define CONFIG_USB_CORE_IP_293A
435 #define CONFIG_USB_GADGET_SC8800G
436 #define CONFIG_USB_DWC
437 #define CONFIG_USB_GADGET_DUALSPEED
438 //#define CONFIG_USB_ETHER
439 #define CONFIG_CMD_FASTBOOT
440 #define SCRATCH_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
441 #define FB_DOWNLOAD_BUF_SIZE (CONFIG_SYS_NAND_U_BOOT_DST - SCRATCH_ADDR-0x800000)
442 #define SCRATCH_ADDR_EXT1 (CONFIG_SYS_NAND_U_BOOT_DST + 32*1024*1024)
443 #define FB_DOWNLOAD_BUF_EXT1_SIZE (224*1024*1024)
445 #define CONFIG_MODEM_CALIBERATE
446 #define CONFIG_MODEM_CALI_UART
450 #define LCD_VDD_2V8_TO_3V0
451 #define CONFIG_DSIH_VERSION_1P21A
452 #define CONFIG_SPLASH_SCREEN
453 #define LCD_BPP LCD_COLOR16
454 //#define CONFIG_LCD_PAD_1024 1
455 //#define CONFIG_LCD_PAD_WXGA 1
456 //#define CONFIG_LCD_HVGA 1
457 //#define CONFIG_LCD_QVGA 1
458 //#define CONFIG_LCD_QHD 1
459 #define CONFIG_LCD_720P 1
460 //#define CONFIG_LCD_INFO
461 //#define LCD_TEST_PATTERN
462 #define CONFIG_LCD_LOGO
463 //#define CONFIG_FB_LCD_S6D0139
464 //#define CONFIG_FB_LCD_HX8389C_MIPI
465 //#define CONFIG_FB_LCD_SSD2075_MIPI
466 //#define CONFIG_FB_LCD_NT35516_MIPI
467 //#define CONFIG_FB_LCD_ILI9486S1_MIPI
468 //#define CONFIG_FB_LCD_VX5B3D_MIPI
469 //#define CONFIG_FB_LCD_NT51017_MIPI
470 //#define CONFIG_FB_LCD_HX8389C_MIPI
471 #define CONFIG_FB_LCD_S6E8AA5X01_MIPI
472 #define CONFIG_SYS_WHITE_ON_BLACK
473 #ifdef LCD_TEST_PATTERN
474 #define CONSOLE_COLOR_RED 0xf800
475 #define CONSOLE_COLOR_GREEN 0x07e0
476 #define CONSOLE_COLOR_YELLOW 0x07e0
477 #define CONSOLE_COLOR_BLUE 0x001f
478 #define CONSOLE_COLOR_MAGENTA 0x001f
479 #define CONSOLE_COLOR_CYAN 0x001f
483 //#define CONFIG_SPRD_SYSDUMP
484 //#include <asm/sizes.h>
485 //#define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_512M - 1))) + SZ_512M - SZ_1M)
486 //#define REAL_SDRAM_SIZE 0x40000000 /*dump 1G */
488 #define CALIBRATE_ENUM_MS 3000
489 #define CALIBRATE_IO_MS 2000
491 //#define LOW_BAT_ADC_LEVEL 782 /*phone battery adc value low than this value will not boot up*/
492 #define LOW_BAT_VOL 3500 /*phone battery voltage low than this value will not boot up*/
493 #define LOW_BAT_VOL_CHG 3300 //3.3V charger connect
495 #define PWR_KEY_DETECT_CNT 12 /*this should match the count of boot_pwr_check() function */
496 #define ALARM_LEAD_SET_MS 0 /* time set for alarm boot in advancd */
498 #define PHYS_OFFSET_ADDR 0x80000000
499 #define TD_CP_OFFSET_ADDR 0x8000000 /*128*/
500 #define TD_CP_SDRAM_SIZE 0x1200000 /*18M*/
501 #define WCDMA_CP_OFFSET_ADDR 0x8000000 /*256M*/
502 #define WCDMA_CP_SDRAM_SIZE 0x1c00000 /*28M*/
503 #define WCN_CP_OFFSET_ADDR 0x0a800000 /*168M*/
504 #define WCN_CP_SDRAM_SIZE 0x201000 /*cp2size*/
506 #define SIPC_APCP_RESET_ADDR_SIZE 0xC00 /*3K*/
507 #define SIPC_APCP_RESET_SIZE 0x1000 /*4K*/
508 #define SIPC_TD_APCP_START_ADDR (PHYS_OFFSET_ADDR + TD_CP_OFFSET_ADDR + TD_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x897FF000*/
509 #define SIPC_WCDMA_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x899F0000*/
510 #define SIPC_WCN_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCN_CP_OFFSET_ADDR + WCN_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x94EFF000*/
511 #define CALIBRATION_FLAG (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - 0x400)
512 #define CALIBRATION_FLAG_WCDMA CALIBRATION_FLAG
514 #define CONFIG_RAM_CONSOLE
516 #ifdef CONFIG_RAM_CONSOLE
517 #define CONFIG_RAM_CONSOLE_SIZE 0x80000
518 #define CONFIG_RAM_CONSOLE_START (CONFIG_SYS_NAND_U_BOOT_START + 0x600000)
520 //#define CALIBRATION_FLAG 0x89700000
522 //#define CONFIG_CMD_SOUND 1
523 //#define CONFIG_CMD_FOR_HTC 1
524 //#define CONFIG_SOUND_CODEC_SPRD_V3 1
525 //#define CONFIG_SOUND_DAI_VBC_R2P0 1
526 /* #define CONFIG_SPRD_AUDIO_DEBUG */
528 #define CONFIG_RAMDUMP_NO_SPLIT 1 /* Don't split sysdump file */
530 #define CONFIG_PBINT_7S_RESET_V1
532 #define CONFIG_7S_RST_MODULE_EN 1 //0:disable module; 1:enable module
534 #define CONFIG_7S_RST_SW_MODE 1 //0:hw reset,1:arm reset,power keep on
535 #define CONFIG_7S_RST_SHORT_MODE 1 //0:long press then release key to trigger;1:press key some time to trigger
536 #define CONFIG_7S_RST_2KEY_MODE 1 //0:1Key--Normal mode; 1:2KEY
537 #define CONFIG_7S_RST_THRESHOLD 7 //7S, hold key down for this time to trigger
539 #define USB_PHY_TUNE_VALUE 0x44073e33
541 /*control the CP need to boot*/
542 #define modem_cp0_enable 1
543 #define modem_cp1_enable 0
544 #define modem_cp2_enable 0
546 //#define CONFIG_SMPL_MODE
547 /* rang:0(0.5s) - 7(4s) unit: s step: 0.5s */
548 /* #define CONFIG_SMPL_THRESHOLD 0 */
550 #define BACKLIGHT_GPIO 214 /*PWM*/
551 #define LCD_LDO_EN_GPIO 167 /*LCD_LDO_EN_GPIO*/
553 #endif /* __CONFIG_H */