Merge git://git.denx.de/u-boot-sunxi
[platform/kernel/u-boot.git] / include / configs / ti816x_evm.h
1 /*
2  * ti816x_evm.h
3  *
4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
5  * Antoine Tenart, <atenart@adeneo-embedded.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #ifndef __CONFIG_TI816X_EVM_H
11 #define __CONFIG_TI816X_EVM_H
12
13 #include <configs/ti_armv7_omap.h>
14 #include <asm/arch/omap.h>
15
16 #define CONFIG_ENV_SIZE                 0x2000
17 #define CONFIG_MACH_TYPE                MACH_TYPE_TI8168EVM
18
19 #define CONFIG_EXTRA_ENV_SETTINGS       \
20         DEFAULT_LINUX_BOOT_ENV \
21         "mtdids=" MTDIDS_DEFAULT "\0" \
22         "mtdparts=" MTDPARTS_DEFAULT "\0" \
23
24 #define CONFIG_BOOTCOMMAND                      \
25         "mmc rescan;"                           \
26         "fatload mmc 0 ${loadaddr} uImage;"     \
27         "bootm ${loadaddr}"                     \
28
29 /* Clock Defines */
30 #define V_OSCK          24000000    /* Clock output from T2 */
31 #define V_SCLK          (V_OSCK >> 1)
32
33 #define CONFIG_CMD_ASKENV
34
35 #define CONFIG_MAX_RAM_BANK_SIZE        (2048 << 20)    /* 2048MB */
36 #define CONFIG_SYS_SDRAM_BASE           0x80000000
37
38 /**
39  * Platform/Board specific defs
40  */
41 #define CONFIG_SYS_CLK_FREQ     27000000
42 #define CONFIG_SYS_TIMERBASE    0x4802E000
43 #define CONFIG_SYS_PTV          2   /* Divisor: 2^(PTV+1) => 8 */
44
45 /*
46  * NS16550 Configuration
47  */
48 #define CONFIG_SYS_NS16550_SERIAL
49 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
50 #define CONFIG_SYS_NS16550_CLK      (48000000)
51 #define CONFIG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
52
53 /* allow overwriting serial config and ethaddr */
54 #define CONFIG_ENV_OVERWRITE
55
56 #define CONFIG_SERIAL1
57 #define CONFIG_SERIAL2
58 #define CONFIG_SERIAL3
59 #define CONFIG_CONS_INDEX       1
60
61 /*
62  * GPMC NAND block.  We support 1 device and the physical address to
63  * access CS0 at is 0x8000000.
64  */
65 #define CONFIG_SYS_NAND_BASE            0x8000000
66 #define CONFIG_SYS_MAX_NAND_DEVICE      1
67
68 /* NAND: SPL related configs */
69 #define CONFIG_SPL_NAND_AM33XX_BCH
70
71 /* NAND: device related configs */
72 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
73 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
74 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
75                                          CONFIG_SYS_NAND_PAGE_SIZE)
76 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
77 #define CONFIG_SYS_NAND_OOBSIZE         64
78 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
79 /* NAND: driver related configs */
80 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
81 #define CONFIG_NAND_OMAP_ELM
82 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
83 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
84                                          10, 11, 12, 13, 14, 15, 16, 17, \
85                                          18, 19, 20, 21, 22, 23, 24, 25, \
86                                          26, 27, 28, 29, 30, 31, 32, 33, \
87                                          34, 35, 36, 37, 38, 39, 40, 41, \
88                                          42, 43, 44, 45, 46, 47, 48, 49, \
89                                          50, 51, 52, 53, 54, 55, 56, 57, }
90
91 #define CONFIG_SYS_NAND_ECCSIZE         512
92 #define CONFIG_SYS_NAND_ECCBYTES        14
93 #define CONFIG_SYS_NAND_ONFI_DETECTION
94 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW
95 #define MTDIDS_DEFAULT                  "nand0=nand.0"
96 #define MTDPARTS_DEFAULT                "mtdparts=nand.0:" \
97                                         "128k(NAND.SPL)," \
98                                         "128k(NAND.SPL.backup1)," \
99                                         "128k(NAND.SPL.backup2)," \
100                                         "128k(NAND.SPL.backup3)," \
101                                         "256k(NAND.u-boot-spl-os)," \
102                                         "1m(NAND.u-boot)," \
103                                         "128k(NAND.u-boot-env)," \
104                                         "128k(NAND.u-boot-env.backup1)," \
105                                         "8m(NAND.kernel)," \
106                                         "-(NAND.file-system)"
107 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x000c0000
108 #define CONFIG_ENV_OFFSET               0x001c0000
109 #define CONFIG_ENV_OFFSET_REDUND        0x001e0000
110 #define CONFIG_SYS_ENV_SECT_SIZE        CONFIG_SYS_NAND_BLOCK_SIZE
111
112 /* SPL */
113 /* Defines for SPL */
114 #define CONFIG_SPL_NAND_AM33XX_BCH      /* ELM support */
115 #define CONFIG_SPL_TEXT_BASE    0x40400000
116 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
117                                          CONFIG_SPL_TEXT_BASE)
118
119 #define CONFIG_SYS_TEXT_BASE        0x80800000
120
121 #define CONFIG_DRIVER_TI_EMAC
122 #define CONFIG_MII
123 #define CONFIG_BOOTP_DNS
124 #define CONFIG_BOOTP_DNS2
125 #define CONFIG_BOOTP_SEND_HOSTNAME
126 #define CONFIG_BOOTP_GATEWAY
127 #define CONFIG_BOOTP_SUBNETMASK
128 #define CONFIG_NET_RETRY_COUNT  10
129
130 /* Since SPL did pll and ddr initialization for us,
131  * we don't need to do it twice.
132  */
133 #ifndef CONFIG_SPL_BUILD
134 #define CONFIG_SKIP_LOWLEVEL_INIT
135 #endif
136
137 /*
138  * Disable MMC DM for SPL build and can be re-enabled after adding
139  * DM support in SPL
140  */
141 #ifdef CONFIG_SPL_BUILD
142 #undef CONFIG_DM_MMC
143 #undef CONFIG_TIMER
144 #undef CONFIG_DM_USB
145 #endif
146 #endif