4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
5 * Antoine Tenart, <atenart@adeneo-embedded.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __CONFIG_TI816X_EVM_H
11 #define __CONFIG_TI816X_EVM_H
16 #define CONFIG_ARCH_CPU_INIT
18 #include <asm/arch/omap.h>
20 #define CONFIG_ENV_SIZE 0x2000
21 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024))
22 #define CONFIG_SYS_LONGHELP /* undef save memory */
23 #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
25 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
26 #define CONFIG_SETUP_MEMORY_TAGS
27 #define CONFIG_INITRD_TAG /* required for ramdisk support */
29 #define CONFIG_EXTRA_ENV_SETTINGS \
30 "loadaddr=0x81000000\0" \
32 #define CONFIG_BOOTCOMMAND \
34 "fatload mmc 0 ${loadaddr} uImage;" \
37 #define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
40 #define V_OSCK 24000000 /* Clock output from T2 */
41 #define V_SCLK (V_OSCK >> 1)
43 #define CONFIG_SYS_MAXARGS 32
44 #define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */
45 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
46 + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
47 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
49 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
51 #define CONFIG_CMD_ASKENV
53 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
54 #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
55 #define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
56 #define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */
57 #define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
59 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
60 #define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
61 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
62 GENERATED_GBL_DATA_SIZE)
65 * Platform/Board specific defs
67 #define CONFIG_SYS_CLK_FREQ 27000000
68 #define CONFIG_SYS_TIMERBASE 0x4802E000
69 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
71 #undef CONFIG_NAND_OMAP_GPMC
74 * NS16550 Configuration
76 #define CONFIG_SYS_NS16550_SERIAL
77 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
78 #define CONFIG_SYS_NS16550_CLK (48000000)
79 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
81 /* allow overwriting serial config and ethaddr */
82 #define CONFIG_ENV_OVERWRITE
84 #define CONFIG_SERIAL1
85 #define CONFIG_SERIAL2
86 #define CONFIG_SERIAL3
87 #define CONFIG_CONS_INDEX 1
89 #define CONFIG_ENV_IS_NOWHERE
93 #define CONFIG_SPL_FRAMEWORK
94 #define CONFIG_SPL_TEXT_BASE 0x40400000
95 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
98 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
99 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
101 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
102 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
104 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
105 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
106 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
108 #define CONFIG_SYS_TEXT_BASE 0x80800000
109 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
110 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
112 /* Since SPL did pll and ddr initialization for us,
113 * we don't need to do it twice.
115 #ifndef CONFIG_SPL_BUILD
116 #define CONFIG_SKIP_LOWLEVEL_INIT