1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
6 * Antoine Tenart, <atenart@adeneo-embedded.com>
9 #ifndef __CONFIG_TI816X_EVM_H
10 #define __CONFIG_TI816X_EVM_H
12 #include <configs/ti_armv7_omap.h>
13 #include <asm/arch/omap.h>
15 #define CONFIG_EXTRA_ENV_SETTINGS \
16 DEFAULT_LINUX_BOOT_ENV \
17 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
18 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
20 #define CONFIG_BOOTCOMMAND \
22 "fatload mmc 0 ${loadaddr} uImage;" \
26 #define V_OSCK 24000000 /* Clock output from T2 */
27 #define V_SCLK (V_OSCK >> 1)
29 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
30 #define CONFIG_SYS_SDRAM_BASE 0x80000000
33 * Platform/Board specific defs
35 #define CONFIG_SYS_CLK_FREQ 27000000
36 #define CONFIG_SYS_TIMERBASE 0x4802E000
37 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
40 * NS16550 Configuration
42 #define CONFIG_SYS_NS16550_SERIAL
43 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
44 #define CONFIG_SYS_NS16550_CLK (48000000)
45 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
47 /* allow overwriting serial config and ethaddr */
51 * GPMC NAND block. We support 1 device and the physical address to
52 * access CS0 at is 0x8000000.
54 #define CONFIG_SYS_NAND_BASE 0x8000000
55 #define CONFIG_SYS_MAX_NAND_DEVICE 1
57 /* NAND: SPL related configs */
59 /* NAND: device related configs */
60 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
61 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
62 CONFIG_SYS_NAND_PAGE_SIZE)
63 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
64 #define CONFIG_SYS_NAND_OOBSIZE 64
65 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
66 /* NAND: driver related configs */
67 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
68 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
69 10, 11, 12, 13, 14, 15, 16, 17, \
70 18, 19, 20, 21, 22, 23, 24, 25, \
71 26, 27, 28, 29, 30, 31, 32, 33, \
72 34, 35, 36, 37, 38, 39, 40, 41, \
73 42, 43, 44, 45, 46, 47, 48, 49, \
74 50, 51, 52, 53, 54, 55, 56, 57, }
76 #define CONFIG_SYS_NAND_ECCSIZE 512
77 #define CONFIG_SYS_NAND_ECCBYTES 14
78 #define CONFIG_SYS_NAND_ONFI_DETECTION
79 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
80 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
81 #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
85 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
88 #define CONFIG_NET_RETRY_COUNT 10
90 /* Since SPL did pll and ddr initialization for us,
91 * we don't need to do it twice.
95 * Disable MMC DM for SPL build and can be re-enabled after adding
98 #ifdef CONFIG_SPL_BUILD