1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
6 * Antoine Tenart, <atenart@adeneo-embedded.com>
9 #ifndef __CONFIG_TI816X_EVM_H
10 #define __CONFIG_TI816X_EVM_H
12 #include <configs/ti_armv7_omap.h>
13 #include <asm/arch/omap.h>
15 #define CONFIG_EXTRA_ENV_SETTINGS \
16 DEFAULT_LINUX_BOOT_ENV \
17 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
18 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
21 #define V_OSCK 24000000 /* Clock output from T2 */
22 #define V_SCLK (V_OSCK >> 1)
24 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
25 #define CONFIG_SYS_SDRAM_BASE 0x80000000
28 * Platform/Board specific defs
30 #define CONFIG_SYS_TIMERBASE 0x4802E000
31 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
34 * NS16550 Configuration
36 #define CONFIG_SYS_NS16550_SERIAL
37 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
38 #define CONFIG_SYS_NS16550_CLK (48000000)
39 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
41 /* allow overwriting serial config and ethaddr */
45 * GPMC NAND block. We support 1 device and the physical address to
46 * access CS0 at is 0x8000000.
48 #define CONFIG_SYS_NAND_BASE 0x8000000
49 #define CONFIG_SYS_MAX_NAND_DEVICE 1
51 /* NAND: SPL related configs */
53 /* NAND: device related configs */
54 /* NAND: driver related configs */
55 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
56 10, 11, 12, 13, 14, 15, 16, 17, \
57 18, 19, 20, 21, 22, 23, 24, 25, \
58 26, 27, 28, 29, 30, 31, 32, 33, \
59 34, 35, 36, 37, 38, 39, 40, 41, \
60 42, 43, 44, 45, 46, 47, 48, 49, \
61 50, 51, 52, 53, 54, 55, 56, 57, }
63 #define CONFIG_SYS_NAND_ECCSIZE 512
64 #define CONFIG_SYS_NAND_ECCBYTES 14
68 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
71 #define CONFIG_NET_RETRY_COUNT 10
73 /* Since SPL did pll and ddr initialization for us,
74 * we don't need to do it twice.
78 * Disable MMC DM for SPL build and can be re-enabled after adding
81 #ifdef CONFIG_SPL_BUILD