1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014, Cavium Inc.
6 #ifndef __THUNDERX_88XX_H__
7 #define __THUNDERX_88XX_H__
9 #define CONFIG_REMAKE_ELF
11 #define CONFIG_THUNDERX
13 #define CONFIG_SYS_64BIT
15 #define MEM_BASE 0x00500000
17 #define CONFIG_SYS_LOWMEM_BASE MEM_BASE
19 /* Link Definitions */
20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
22 /* SMP Spin Table Definitions */
23 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
25 /* Generic Timer Definitions */
26 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
28 #define CONFIG_SYS_MEMTEST_START MEM_BASE
29 #define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE)
31 /* Size of malloc() pool */
32 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
34 /* PL011 Serial Configuration */
36 #define CONFIG_PL011_CLOCK 24000000
38 /* Generic Interrupt Controller Definitions */
39 #define GICD_BASE (0x801000000000)
40 #define GICR_BASE (0x801000002000)
41 #define CONFIG_SYS_SERIAL0 0x87e024000000
42 #define CONFIG_SYS_SERIAL1 0x87e025000000
45 #define CONFIG_BOOTP_BOOTFILESIZE
47 /* Miscellaneous configurable options */
48 #define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
50 /* Physical Memory Map */
51 #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
52 #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
53 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
55 /* Initial environment variables */
56 #define UBOOT_IMG_HEAD_SIZE 0x40
58 #define CONFIG_EXTRA_ENV_SETTINGS \
59 "kernel_addr=08007ffc0\0" \
60 "fdt_addr=0x94C00000\0" \
61 "fdt_high=0x9fffffff\0"
63 /* Do not preserve environment */
64 #define CONFIG_ENV_SIZE 0x1000
66 /* Monitor Command Prompt */
67 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
68 #define CONFIG_SYS_MAXARGS 64 /* max command args */
69 #define CONFIG_NO_RELOCATION 1
70 #define PLL_REF_CLK 50000000 /* 50 MHz */
71 #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
73 #endif /* __THUNDERX_88XX_H__ */