1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014, Cavium Inc.
6 #ifndef __THUNDERX_88XX_H__
7 #define __THUNDERX_88XX_H__
9 #define CONFIG_THUNDERX
11 #define CONFIG_SYS_64BIT
13 #define MEM_BASE 0x00500000
15 #define CONFIG_SYS_LOWMEM_BASE MEM_BASE
17 /* Link Definitions */
18 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
20 /* SMP Spin Table Definitions */
21 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
23 /* PL011 Serial Configuration */
25 #define CONFIG_PL011_CLOCK 24000000
27 /* Generic Interrupt Controller Definitions */
28 #define GICD_BASE (0x801000000000)
29 #define GICR_BASE (0x801000002000)
30 #define CONFIG_SYS_SERIAL0 0x87e024000000
31 #define CONFIG_SYS_SERIAL1 0x87e025000000
33 /* Miscellaneous configurable options */
35 /* Physical Memory Map */
36 #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
37 #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
38 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
40 /* Initial environment variables */
41 #define UBOOT_IMG_HEAD_SIZE 0x40
43 #define CONFIG_EXTRA_ENV_SETTINGS \
44 "kernel_addr=08007ffc0\0" \
45 "fdt_addr=0x94C00000\0" \
46 "fdt_high=0x9fffffff\0"
48 /* Do not preserve environment */
50 #define PLL_REF_CLK 50000000 /* 50 MHz */
51 #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
53 #endif /* __THUNDERX_88XX_H__ */