1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
6 #ifndef _CONFIG_THEADORABLE_H
7 #define _CONFIG_THEADORABLE_H
10 * High Level Configuration Options (easy to change)
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
20 * The debugging version enables USB support via defconfig.
21 * This version should also enable all other non-production
22 * interfaces / features.
26 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
27 #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
29 /* USB/EHCI configuration */
30 #define CONFIG_EHCI_IS_TDI
31 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
33 /* Environment in SPI NOR flash */
35 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
37 /* Keep device tree and initrd in lower memory so the kernel can access them */
38 #define CONFIG_EXTRA_ENV_SETTINGS \
39 "fdt_high=0x10000000\0" \
40 "initrd_high=0x10000000\0"
43 #define CONFIG_SYS_SATA_MAX_DEVICE 1
46 /* Enable LCD and reserve 512KB from top of memory*/
47 #define CONFIG_SYS_MEM_TOP_HIDE 0x80000
49 /* FPGA programming support */
50 #define CONFIG_FPGA_STRATIX_V
55 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
56 #define BOOTCOUNT_ADDR 0x1000
59 * mv-common.h should be defined after CMD configs since it used them
60 * to enable certain macros
62 #include "mv-common.h"
65 * Memory layout while starting into the bin_hdr via the
68 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
69 * 0x4000.4030 bin_hdr start address
70 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
71 * 0x4007.fffc BootROM stack top
73 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
74 * L2 cache thus cannot be used.
79 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
81 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
82 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
84 #ifdef CONFIG_SPL_BUILD
85 #define CONFIG_SYS_MALLOC_SIMPLE
88 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
89 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
91 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
92 #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
94 #endif /* _CONFIG_THEADORABLE_H */