2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CONFIG_THEADORABLE_H
8 #define _CONFIG_THEADORABLE_H
11 * High Level Configuration Options (easy to change)
13 #define CONFIG_DISPLAY_BOARDINFO_LATE
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
20 #define CONFIG_SYS_TEXT_BASE 0x00800000
21 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
24 * Commands configuration
26 #define CONFIG_CMD_BOOTZ
27 #define CONFIG_CMD_CACHE
28 #define CONFIG_CMD_ENV
29 #define CONFIG_CMD_EXT2
30 #define CONFIG_CMD_EXT4
31 #define CONFIG_CMD_FAT
32 #define CONFIG_CMD_FS_GENERIC
33 #define CONFIG_CMD_I2C
34 #define CONFIG_CMD_SATA
35 #define CONFIG_CMD_TIME
38 * The debugging version enables USB support via defconfig.
39 * This version should also enable all other non-production
40 * interfaces / features.
43 #define CONFIG_CMD_DHCP
44 #define CONFIG_CMD_PCI
45 #define CONFIG_CMD_PING
46 #define CONFIG_CMD_SPI
47 #define CONFIG_CMD_TFTPPUT
51 #define CONFIG_SYS_I2C
52 #define CONFIG_SYS_I2C_MVTWSI
53 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
54 #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
55 #define CONFIG_SYS_I2C_SLAVE 0x0
56 #define CONFIG_SYS_I2C_SPEED 100000
58 /* USB/EHCI configuration */
59 #define CONFIG_EHCI_IS_TDI
60 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
62 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
64 /* SPI NOR flash default params, used by sf commands */
65 #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */
66 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
68 /* Environment in SPI NOR flash */
69 #define CONFIG_ENV_IS_IN_SPI_FLASH
70 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
71 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
72 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
73 #define CONFIG_ENV_OVERWRITE
75 #define CONFIG_PHY_MARVELL /* there is a marvell phy */
76 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
78 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
79 #define CONFIG_SYS_ALT_MEMTEST
80 #define CONFIG_PREBOOT
82 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
83 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
85 /* Keep device tree and initrd in lower memory so the kernel can access them */
86 #define CONFIG_EXTRA_ENV_SETTINGS \
87 "fdt_high=0x10000000\0" \
88 "initrd_high=0x10000000\0"
91 #define CONFIG_SYS_SATA_MAX_DEVICE 1
92 #define CONFIG_SATA_MV
95 #define CONFIG_EFI_PARTITION
96 #define CONFIG_DOS_PARTITION
98 /* Additional FS support/configuration */
99 #define CONFIG_SUPPORT_VFAT
102 #ifdef CONFIG_CMD_PCI
103 #ifndef CONFIG_SPL_BUILD
105 #define CONFIG_PCI_MVEBU
106 #define CONFIG_PCI_PNP
107 #define CONFIG_BOARD_LATE_INIT /* for PEX switch test */
111 /* Enable LCD and reserve 512KB from top of memory*/
112 #define CONFIG_SYS_MEM_TOP_HIDE 0x80000
115 #define CONFIG_CFB_CONSOLE
116 #define CONFIG_VGA_AS_SINGLE_DEVICE
117 #define CONFIG_CMD_BMP
119 /* FPGA programming support */
121 #define CONFIG_FPGA_ALTERA
122 #define CONFIG_FPGA_STRATIX_V
127 #define CONFIG_BOOTCOUNT_LIMIT
128 #define CONFIG_BOOTCOUNT_RAM
129 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
130 #define BOOTCOUNT_ADDR 0x1000
133 * mv-common.h should be defined after CMD configs since it used them
134 * to enable certain macros
136 #include "mv-common.h"
139 * Memory layout while starting into the bin_hdr via the
142 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
143 * 0x4000.4030 bin_hdr start address
144 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
145 * 0x4007.fffc BootROM stack top
147 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
148 * L2 cache thus cannot be used.
152 /* Defines for SPL */
153 #define CONFIG_SPL_FRAMEWORK
154 #define CONFIG_SPL_TEXT_BASE 0x40004030
155 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
157 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
158 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
160 #ifdef CONFIG_SPL_BUILD
161 #define CONFIG_SYS_MALLOC_SIMPLE
164 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
165 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
167 #define CONFIG_SPL_LIBCOMMON_SUPPORT
168 #define CONFIG_SPL_LIBGENERIC_SUPPORT
169 #define CONFIG_SPL_SERIAL_SUPPORT
170 #define CONFIG_SPL_I2C_SUPPORT
172 /* SPL related SPI defines */
173 #define CONFIG_SPL_SPI_SUPPORT
174 #define CONFIG_SPL_SPI_FLASH_SUPPORT
175 #define CONFIG_SPL_SPI_LOAD
176 #define CONFIG_SPL_SPI_BUS 0
177 #define CONFIG_SPL_SPI_CS 0
178 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
179 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
181 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
182 #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
184 #endif /* _CONFIG_THEADORABLE_H */