1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
6 #ifndef _CONFIG_THEADORABLE_H
7 #define _CONFIG_THEADORABLE_H
9 #include <linux/sizes.h>
12 * High Level Configuration Options (easy to change)
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
22 * The debugging version enables USB support via defconfig.
23 * This version should also enable all other non-production
24 * interfaces / features.
28 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
29 #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
31 /* USB/EHCI configuration */
33 /* Environment in SPI NOR flash */
35 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
37 /* Keep device tree and initrd in lower memory so the kernel can access them */
38 #define CFG_EXTRA_ENV_SETTINGS \
39 "fdt_high=0x10000000\0" \
40 "initrd_high=0x10000000\0"
45 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
46 #define BOOTCOUNT_ADDR 0x1000
49 * mv-common.h should be defined after CMD configs since it used them
50 * to enable certain macros
52 #include "mv-common.h"
55 * Memory layout while starting into the bin_hdr via the
58 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
59 * 0x4000.4030 bin_hdr start address
60 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
61 * 0x4007.fffc BootROM stack top
63 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
64 * L2 cache thus cannot be used.
70 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
71 #define CFG_SYS_SDRAM_SIZE SZ_2G
73 #endif /* _CONFIG_THEADORABLE_H */