2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef __TEGRA20_COMMON_H
25 #define __TEGRA20_COMMON_H
26 #include <asm/sizes.h>
27 #include <linux/stringify.h>
30 * High Level Configuration Options
32 #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
33 #define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
34 #define CONFIG_TEGRA /* which is a Tegra generic machine */
35 #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
37 #define CONFIG_SYS_CACHELINE_SIZE 32
39 #include <asm/arch/tegra.h> /* get chip and board defs */
42 * Display CPU and Board information
44 #define CONFIG_DISPLAY_CPUINFO
45 #define CONFIG_DISPLAY_BOARDINFO
47 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
48 #define CONFIG_OF_LIBFDT /* enable passing of devicetree */
50 #ifdef CONFIG_TEGRA_LP0
51 #define TEGRA_LP0_ADDR 0x1C406000
52 #define TEGRA_LP0_SIZE 0x2000
53 #define TEGRA_LP0_VEC \
54 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
55 "@" __stringify(TEGRA_LP0_ADDR) " "
61 #define CONFIG_ENV_VARS_UBOOT_CONFIG
62 #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
65 * Size of malloc() pool
67 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
72 #define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
75 * NS16550 Configuration
77 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
79 #define CONFIG_SYS_NS16550
80 #define CONFIG_SYS_NS16550_SERIAL
81 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
82 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
85 * select serial console configuration
87 #define CONFIG_CONS_INDEX 1
89 /* allow to overwrite serial and ethaddr */
90 #define CONFIG_ENV_OVERWRITE
91 #define CONFIG_BAUDRATE 115200
92 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
96 * This parameter affects a TXFILLTUNING field that controls how much data is
97 * sent to the latency fifo before it is sent to the wire. Without this
98 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
99 * packets depending on the buffer address and size.
101 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10
102 #define CONFIG_EHCI_IS_TDI
103 #define CONFIG_EHCI_DCACHE
105 /* Total I2C ports on Tegra20 */
106 #define TEGRA_I2C_NUM_CONTROLLERS 4
108 /* include default commands */
109 #include <config_cmd_default.h>
110 #define CONFIG_PARTITION_UUIDS
111 #define CONFIG_CMD_PART
113 /* remove unused commands */
114 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
115 #undef CONFIG_CMD_FPGA /* FPGA configuration support */
116 #undef CONFIG_CMD_IMI
117 #undef CONFIG_CMD_IMLS
118 #undef CONFIG_CMD_NFS /* NFS support */
119 #undef CONFIG_CMD_NET /* network support */
121 /* turn on command-line edit/hist/auto */
122 #define CONFIG_CMDLINE_EDITING
123 #define CONFIG_COMMAND_HISTORY
124 #define CONFIG_AUTO_COMPLETE
126 #define CONFIG_SYS_NO_FLASH
128 /* Environment information, boards can override if required */
129 #define CONFIG_CONSOLE_MUX
130 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
131 #define TEGRA_DEVICE_SETTINGS "stdin=serial\0" \
135 #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
136 #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
139 * Miscellaneous configurable options
141 #define CONFIG_SYS_LONGHELP /* undef to save memory */
142 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
143 #define CONFIG_SYS_PROMPT V_PROMPT
145 * Increasing the size of the IO buffer as default nfsargs size is more
146 * than 256 and so it is not possible to edit it
148 #define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
149 /* Print Buffer Size */
150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
151 sizeof(CONFIG_SYS_PROMPT) + 16)
152 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
153 /* Boot Argument Buffer Size */
154 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
156 #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
157 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
159 #define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
160 #define CONFIG_SYS_HZ 1000
162 #define CONFIG_STACKBASE 0x2800000 /* 40MB */
164 /*-----------------------------------------------------------------------
165 * Physical Memory Map
167 #define CONFIG_NR_DRAM_BANKS 1
168 #define PHYS_SDRAM_1 NV_PA_SDRC_CS0
169 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
171 #define CONFIG_SYS_TEXT_BASE 0x0010c000
172 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
173 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
175 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
177 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
178 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
179 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
180 CONFIG_SYS_INIT_RAM_SIZE - \
181 GENERATED_GBL_DATA_SIZE)
183 #define CONFIG_TEGRA_GPIO
184 #define CONFIG_CMD_GPIO
185 #define CONFIG_CMD_ENTERRCM
186 #define CONFIG_CMD_BOOTZ
188 /* Defines for SPL */
190 #define CONFIG_SPL_FRAMEWORK
191 #define CONFIG_SPL_RAM_DEVICE
192 #define CONFIG_SPL_BOARD_INIT
193 #define CONFIG_SPL_NAND_SIMPLE
194 #define CONFIG_SPL_TEXT_BASE 0x00108000
195 #define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
196 CONFIG_SPL_TEXT_BASE)
197 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000
198 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
199 #define CONFIG_SPL_STACK 0x000ffffc
201 #define CONFIG_SPL_LIBCOMMON_SUPPORT
202 #define CONFIG_SPL_LIBGENERIC_SUPPORT
203 #define CONFIG_SPL_SERIAL_SUPPORT
204 #define CONFIG_SPL_GPIO_SUPPORT
205 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
207 #define CONFIG_SYS_NAND_SELF_INIT
208 #define CONFIG_SYS_NAND_ONFI_DETECTION
210 #endif /* __TEGRA20_COMMON_H */