1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2012
4 * NVIDIA Corporation <www.nvidia.com>
7 #ifndef _TEGRA_COMMON_H_
8 #define _TEGRA_COMMON_H_
9 #include <linux/sizes.h>
10 #include <linux/stringify.h>
13 * High Level Configuration Options
16 #include <asm/arch/tegra.h> /* get chip and board defs */
18 /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
20 #define CONFIG_SYS_TIMER_RATE 1000000
21 #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
27 * NS16550 Configuration
29 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
32 * Common HW configuration.
33 * If this varies between SoCs later, move to tegraNN-common.h
34 * Note: This is number of devices, not max device ID.
36 #define CONFIG_SYS_MMC_MAX_DEVICE 4
38 /* Boot Argument Buffer Size */
39 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
42 #define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
44 #define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
47 /*-----------------------------------------------------------------------
50 #define PHYS_SDRAM_1 NV_PA_SDRC_CS0
51 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
53 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
55 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
58 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
59 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
60 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
61 CONFIG_SYS_INIT_RAM_SIZE - \
62 GENERATED_GBL_DATA_SIZE)
67 #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
69 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
72 #endif /* _TEGRA_COMMON_H_ */