1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2012
4 * NVIDIA Corporation <www.nvidia.com>
7 #ifndef _TEGRA_COMMON_H_
8 #define _TEGRA_COMMON_H_
9 #include <linux/sizes.h>
10 #include <linux/stringify.h>
13 * High Level Configuration Options
15 #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
17 #include <asm/arch/tegra.h> /* get chip and board defs */
19 /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
21 #define CONFIG_SYS_TIMER_RATE 1000000
22 #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
25 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
30 * NS16550 Configuration
32 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
35 * Common HW configuration.
36 * If this varies between SoCs later, move to tegraNN-common.h
37 * Note: This is number of devices, not max device ID.
39 #define CONFIG_SYS_MMC_MAX_DEVICE 4
42 * Increasing the size of the IO buffer as default nfsargs size is more
43 * than 256 and so it is not possible to edit it
45 #define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */
46 /* Print Buffer Size */
47 #define CONFIG_SYS_MAXARGS 64 /* max number of command args */
49 /* Boot Argument Buffer Size */
50 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
52 /*-----------------------------------------------------------------------
55 #define PHYS_SDRAM_1 NV_PA_SDRC_CS0
56 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
58 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
60 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
63 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
64 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
65 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
66 CONFIG_SYS_INIT_RAM_SIZE - \
67 GENERATED_GBL_DATA_SIZE)
72 #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
74 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
77 #endif /* _TEGRA_COMMON_H_ */