2 * Copyright (C) 2014 Soeren Moch <smoch@web.de>
4 * Configuration settings for the TBS2910 MatrixARM board.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __TBS2910_CONFIG_H
10 #define __TBS2910_CONFIG_H
12 #include "mx6_common.h"
14 /* General configuration */
15 #define CONFIG_SYS_THUMB_BUILD
17 #define CONFIG_MACH_TYPE 3980
19 #define CONFIG_BOARD_EARLY_INIT_F
21 #define CONFIG_SYS_HZ 1000
23 #define CONFIG_IMX_THERMAL
25 /* Physical Memory Map */
26 #define CONFIG_NR_DRAM_BANKS 1
27 #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
29 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
30 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
31 #define CONFIG_SYS_INIT_SP_OFFSET \
32 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
33 #define CONFIG_SYS_INIT_SP_ADDR \
34 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
36 #define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
38 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
39 #define CONFIG_SYS_MEMTEST_END \
40 (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
42 #define CONFIG_SYS_BOOTMAPSZ 0x6C000000
45 #define CONFIG_MXC_UART
46 #define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
47 #define CONFIG_BAUDRATE 115200
49 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
50 #define CONFIG_CONSOLE_MUX
51 #define CONFIG_CONS_INDEX 1
53 #define CONFIG_PRE_CONSOLE_BUFFER
54 #define CONFIG_PRE_CON_BUF_SZ 4096
55 #define CONFIG_PRE_CON_BUF_ADDR 0x7C000000
57 /* *** Command definition *** */
58 #define CONFIG_CMD_BMODE
59 #define CONFIG_CMD_MEMTEST
60 #define CONFIG_CMD_TIME
62 /* Filesystems / image support */
63 #define CONFIG_EFI_PARTITION
66 #define CONFIG_SYS_FSL_USDHC_NUM 3
67 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
68 #define CONFIG_SUPPORT_EMMC_BOOT
71 #define CONFIG_FEC_MXC
72 #define CONFIG_CMD_PING
73 #define CONFIG_CMD_DHCP
74 #define CONFIG_CMD_MII
75 #define CONFIG_FEC_MXC
77 #define IMX_FEC_BASE ENET_BASE_ADDR
78 #define CONFIG_FEC_XCV_TYPE RGMII
79 #define CONFIG_ETHPRIME "FEC"
80 #define CONFIG_FEC_MXC_PHYADDR 4
82 #define CONFIG_PHY_ATHEROS
87 #define CONFIG_VIDEO_IPUV3
88 #define CONFIG_IPUV3_CLK 260000000
89 #define CONFIG_CFB_CONSOLE
90 #define CONFIG_CFB_CONSOLE_ANSI
91 #define CONFIG_VIDEO_SW_CURSOR
92 #define CONFIG_VGA_AS_SINGLE_DEVICE
93 #define CONFIG_VIDEO_BMP_RLE8
94 #define CONFIG_IMX_HDMI
95 #define CONFIG_IMX_VIDEO_SKIP
96 #define CONFIG_CMD_HDMIDETECT
100 #define CONFIG_CMD_PCI
101 #ifdef CONFIG_CMD_PCI
103 #define CONFIG_PCI_PNP
104 #define CONFIG_PCI_SCAN_SHOW
105 #define CONFIG_PCIE_IMX
106 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
110 #define CONFIG_CMD_SATA
111 #ifdef CONFIG_CMD_SATA
112 #define CONFIG_DWC_AHSATA
113 #define CONFIG_SYS_SATA_MAX_DEVICE 1
114 #define CONFIG_DWC_AHSATA_PORT_ID 0
115 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
117 #define CONFIG_LIBATA
121 #define CONFIG_CMD_USB
122 #ifdef CONFIG_CMD_USB
123 #define CONFIG_USB_EHCI
124 #define CONFIG_USB_EHCI_MX6
125 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
126 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
127 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
128 #define CONFIG_USB_STORAGE
129 #define CONFIG_CMD_USB_MASS_STORAGE
130 #ifdef CONFIG_CMD_USB_MASS_STORAGE
131 #define CONFIG_CI_UDC
132 #define CONFIG_USBD_HS
133 #define CONFIG_USB_GADGET
134 #define CONFIG_USB_FUNCTION_MASS_STORAGE
135 #define CONFIG_USB_GADGET_DUALSPEED
136 #define CONFIG_USB_GADGET_VBUS_DRAW 0
137 #define CONFIG_USB_GADGET_DOWNLOAD
138 #define CONFIG_G_DNL_VENDOR_NUM 0x0525
139 #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
140 #define CONFIG_G_DNL_MANUFACTURER "TBS"
141 #endif /* CONFIG_CMD_USB_MASS_STORAGE */
142 #define CONFIG_USB_KEYBOARD
143 #ifdef CONFIG_USB_KEYBOARD
144 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
145 #define CONFIG_SYS_STDIO_DEREGISTER
146 #define CONFIG_PREBOOT \
147 "if hdmidet; then " \
149 "run set_con_usb_hdmi; " \
151 "run set_con_serial; " \
153 #endif /* CONFIG_USB_KEYBOARD */
154 #endif /* CONFIG_CMD_USB */
157 #define CONFIG_CMD_DATE
158 #ifdef CONFIG_CMD_DATE
159 #define CONFIG_CMD_I2C
160 #define CONFIG_RTC_DS1307
161 #define CONFIG_SYS_RTC_BUS_NUM 2
165 #define CONFIG_CMD_I2C
166 #ifdef CONFIG_CMD_I2C
167 #define CONFIG_SYS_I2C
168 #define CONFIG_SYS_I2C_MXC
169 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
170 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
171 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
172 #define CONFIG_SYS_I2C_SPEED 100000
173 #define CONFIG_I2C_EDID
176 /* Environment organization */
177 #define CONFIG_ENV_IS_IN_MMC
178 #define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */
179 #define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */
180 #define CONFIG_ENV_SIZE (8 * 1024)
181 #define CONFIG_ENV_OFFSET (384 * 1024)
182 #define CONFIG_ENV_OVERWRITE
184 #define CONFIG_EXTRA_ENV_SETTINGS \
185 "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
186 "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
187 "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
188 "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
189 "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
190 "${bootargs_mmc3}\0" \
191 "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
192 "rdinit=/sbin/init enable_wait_mode=off\0" \
193 "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
194 "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \
195 "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
196 "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
197 "run bootargs_upd; " \
198 "bootm 0x10800000 0x10d00000\0" \
199 "console=ttymxc0\0" \
200 "fan=gpio set 92\0" \
201 "set_con_serial=setenv stdin serial; " \
202 "setenv stdout serial; " \
203 "setenv stderr serial;\0" \
204 "set_con_usb_hdmi=setenv stdin serial,usbkbd; " \
205 "setenv stdout serial,vga; " \
206 "setenv stderr serial,vga;\0"
208 #define CONFIG_BOOTCOMMAND \
210 "if run bootcmd_up1; then " \
211 "run bootcmd_up2; " \
213 "run bootcmd_mmc; " \
216 #endif /* __TBS2910_CONFIG_H * */