1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuration settings for the TechNexion TAO-3530 SOM
4 * equipped on Thunder baseboard.
6 * Edward Lin <linuxfae@technexion.com>
7 * Tapani Utriainen <linuxfae@technexion.com>
9 * Copyright (C) 2013 Stefan Roese <sr@denx.de>
16 * High Level Configuration Options
19 #include <asm/arch/cpu.h> /* get chip and board defs */
20 #include <asm/arch/omap.h>
23 #define V_OSCK 26000000 /* Clock output from T2 */
24 #define V_SCLK (V_OSCK >> 1)
26 #define CONFIG_CMDLINE_TAG
27 #define CONFIG_SETUP_MEMORY_TAGS
28 #define CONFIG_INITRD_TAG
29 #define CONFIG_REVISION_TAG
32 * Size of malloc() pool
34 #define CONFIG_SYS_MALLOC_LEN (4 << 20)
35 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
42 * NS16550 Configuration
44 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
46 #define CONFIG_SYS_NS16550_SERIAL
47 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
48 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
51 * select serial console configuration
53 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
55 /* allow to overwrite serial and ethaddr */
56 #define CONFIG_ENV_OVERWRITE
58 /* commands to include */
60 #define CONFIG_SYS_I2C
61 #define CONFIG_I2C_MULTI_BUS
66 #define CONFIG_TWL4030_LED
71 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
72 /* to access nand at */
75 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
77 /* Environment information */
79 #define CONFIG_EXTRA_ENV_SETTINGS \
80 "loadaddr=0x82000000\0" \
81 "console=ttyO2,115200n8\0" \
83 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
84 "tv_mode=omapfb.mode=tv:ntsc\0" \
85 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
86 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
89 "mmcroot=/dev/mmcblk0p2 rw\0" \
90 "mmcrootfstype=ext3 rootwait\0" \
91 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
92 "nandrootfstype=ubifs\0" \
93 "mmcargs=setenv bootargs console=${console} " \
94 "mpurate=${mpurate} " \
97 "rootfstype=${mmcrootfstype} " \
98 "${extra_options}\0" \
99 "nandargs=setenv bootargs console=${console} " \
100 "mpurate=${mpurate} " \
102 "${network_setting} " \
103 "root=${nandroot} " \
104 "rootfstype=${nandrootfstype} "\
105 "${extra_options}\0" \
106 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
107 "bootscript=echo Running bootscript from mmc ...; " \
108 "source ${loadaddr}\0" \
109 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
110 "mmcboot=echo Booting from mmc ...; " \
112 "bootm ${loadaddr}\0" \
113 "nandboot=echo Booting from nand ...; " \
115 "nand read ${loadaddr} 280000 400000; " \
116 "bootm ${loadaddr}\0" \
118 #define CONFIG_BOOTCOMMAND \
119 "if mmc rescan ${mmcdev}; then " \
120 "if run loadbootscript; then " \
123 "if run loaduimage; then " \
125 "else run nandboot; " \
128 "else run nandboot; fi"
131 * Miscellaneous configurable options
134 /* turn on command-line edit/hist/auto */
136 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
138 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
139 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
141 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
145 * OMAP3 has 12 GP timers, they can be driven by the system clock
146 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
147 * This rate is divided by a local divisor.
149 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
150 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
153 * Physical Memory Map
155 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
156 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
157 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
160 * FLASH and environment organization
163 /* **** PISMO SUPPORT *** */
164 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
165 #define CONFIG_SYS_FLASH_BASE NAND_BASE
167 /* Monitor at start of flash */
168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
169 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
171 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
173 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
174 #define CONFIG_ENV_OFFSET 0x260000
175 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
177 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
178 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
179 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
180 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
181 CONFIG_SYS_INIT_RAM_SIZE - \
182 GENERATED_GBL_DATA_SIZE)
187 * Currently only EHCI is enabled, the MUSB OTG controller
192 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
194 /* Defines for SPL */
196 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
197 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
199 #define CONFIG_SPL_NAND_BASE
200 #define CONFIG_SPL_NAND_DRIVERS
201 #define CONFIG_SPL_NAND_ECC
203 /* NAND boot config */
204 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
205 #define CONFIG_SYS_NAND_PAGE_COUNT 64
206 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
207 #define CONFIG_SYS_NAND_OOBSIZE 64
208 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
209 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
211 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
212 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
214 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
216 #define CONFIG_SYS_NAND_ECCSIZE 512
217 #define CONFIG_SYS_NAND_ECCBYTES 3
218 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
220 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
221 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
223 #define CONFIG_SPL_TEXT_BASE 0x40200800
224 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
225 CONFIG_SPL_TEXT_BASE)
228 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
229 * older x-loader implementations. And move the BSS area so that it
230 * doesn't overlap with TEXT_BASE.
232 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
233 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
235 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
236 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
238 #endif /* __CONFIG_H */