include/configs/tao3530.h

   1 /*
   2  * Configuration settings for the TechNexion TAO-3530 SOM
   3  * equipped on Thunder baseboard.
   4  *
   5  * Edward Lin <linuxfae@technexion.com>
   6  * Tapani Utriainen <linuxfae@technexion.com>
   7  *
   8  * Copyright (C) 2013 Stefan Roese <sr@denx.de>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_OMAP_GPIO
  20
  21 #define CONFIG_SDRC                     /* Has an SDRC controller */
  22
  23 #include <asm/arch/cpu.h>               /* get chip and board defs */
  24 #include <asm/arch/omap.h>
  25
  26 /* Clock Defines */
  27 #define V_OSCK                  26000000        /* Clock output from T2 */
  28 #define V_SCLK                  (V_OSCK >> 1)
  29
  30 #define CONFIG_MISC_INIT_R
  31
  32 #define CONFIG_CMDLINE_TAG
  33 #define CONFIG_SETUP_MEMORY_TAGS
  34 #define CONFIG_INITRD_TAG
  35 #define CONFIG_REVISION_TAG
  36
  37 /*
  38  * Size of malloc() pool
  39  */
  40 #define CONFIG_SYS_MALLOC_LEN           (4 << 20)
  41 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  42
  43 /*
  44  * Hardware drivers
  45  */
  46
  47 /*
  48  * NS16550 Configuration
  49  */
  50 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  51
  52 #define CONFIG_SYS_NS16550_SERIAL
  53 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  54 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  55
  56 /*
  57  * select serial console configuration
  58  */
  59 #define CONFIG_CONS_INDEX               3
  60 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  61
  62 /* allow to overwrite serial and ethaddr */
  63 #define CONFIG_ENV_OVERWRITE
  64
  65 /* GPIO banks */
  66 #define CONFIG_OMAP3_GPIO_2             /* GPIO32 ..63  is in GPIO bank 2 */
  67 #define CONFIG_OMAP3_GPIO_3             /* GPIO64 ..95  is in GPIO bank 3 */
  68 #define CONFIG_OMAP3_GPIO_4             /* GPIO96 ..127 is in GPIO bank 4 */
  69 #define CONFIG_OMAP3_GPIO_5             /* GPIO128..159 is in GPIO bank 5 */
  70 #define CONFIG_OMAP3_GPIO_6             /* GPIO160..191 is in GPIO bank 6 */
  71
  72 /* commands to include */
  73 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
  74 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
  75 #define MTDIDS_DEFAULT                  "nand0=nand"
  76 #define MTDPARTS_DEFAULT                "mtdparts=nand:512k(x-loader),"\
  77                                         "1920k(u-boot),128k(u-boot-env),"\
  78                                         "4m(kernel),-(fs)"
  79
  80 #define CONFIG_CMD_NAND         /* NAND support                 */
  81
  82 #define CONFIG_SYS_I2C
  83 #define CONFIG_SYS_I2C_OMAP34XX
  84 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
  85 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
  86 #define CONFIG_I2C_MULTI_BUS
  87
  88 /*
  89  * TWL4030
  90  */
  91 #define CONFIG_TWL4030_LED
  92
  93 /*
  94  * Board NAND Info.
  95  */
  96 #define CONFIG_NAND_OMAP_GPMC
  97 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
  98                                                         /* to access nand */
  99 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 100                                                         /* to access nand at */
 101                                                         /* CS0 */
 102
 103 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 104                                                         /* devices */
 105 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 106 /* Environment information */
 107
 108 #define CONFIG_EXTRA_ENV_SETTINGS \
 109         "loadaddr=0x82000000\0" \
 110         "console=ttyO2,115200n8\0" \
 111         "mpurate=600\0" \
 112         "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
 113         "tv_mode=omapfb.mode=tv:ntsc\0" \
 114         "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
 115         "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
 116         "extra_options= \0" \
 117         "mmcdev=0\0" \
 118         "mmcroot=/dev/mmcblk0p2 rw\0" \
 119         "mmcrootfstype=ext3 rootwait\0" \
 120         "nandroot=ubi0:rootfs ubi.mtd=4\0" \
 121         "nandrootfstype=ubifs\0" \
 122         "mmcargs=setenv bootargs console=${console} " \
 123                 "mpurate=${mpurate} " \
 124                 "${video_mode} " \
 125                 "root=${mmcroot} " \
 126                 "rootfstype=${mmcrootfstype} " \
 127                 "${extra_options}\0" \
 128         "nandargs=setenv bootargs console=${console} " \
 129                 "mpurate=${mpurate} " \
 130                 "${video_mode} " \
 131                 "${network_setting} " \
 132                 "root=${nandroot} " \
 133                 "rootfstype=${nandrootfstype} "\
 134                 "${extra_options}\0" \
 135         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 136         "bootscript=echo Running bootscript from mmc ...; " \
 137                 "source ${loadaddr}\0" \
 138         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 139         "mmcboot=echo Booting from mmc ...; " \
 140                 "run mmcargs; " \
 141                 "bootm ${loadaddr}\0" \
 142         "nandboot=echo Booting from nand ...; " \
 143                 "run nandargs; " \
 144                 "nand read ${loadaddr} 280000 400000; " \
 145                 "bootm ${loadaddr}\0" \
 146
 147 #define CONFIG_BOOTCOMMAND \
 148         "if mmc rescan ${mmcdev}; then " \
 149                 "if run loadbootscript; then " \
 150                         "run bootscript; " \
 151                 "else " \
 152                         "if run loaduimage; then " \
 153                                 "run mmcboot; " \
 154                         "else run nandboot; " \
 155                         "fi; " \
 156                 "fi; " \
 157         "else run nandboot; fi"
 158
 159 /*
 160  * Miscellaneous configurable options
 161  */
 162 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 163 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 164
 165 /* turn on command-line edit/hist/auto */
 166 #define CONFIG_CMDLINE_EDITING
 167 #define CONFIG_AUTO_COMPLETE
 168
 169 /* Print Buffer Size */
 170 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 171                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 172 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 173 /* Boot Argument Buffer Size */
 174 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 175
 176 #define CONFIG_SYS_ALT_MEMTEST          1
 177 #define CONFIG_SYS_MEMTEST_START        (0x82000000)            /* memtest */
 178                                                                 /* defaults */
 179 #define CONFIG_SYS_MEMTEST_END          (0x83FFFFFF)            /* 64MB */
 180 #define CONFIG_SYS_MEMTEST_SCRATCH      (0x81000000)    /* dummy address */
 181
 182 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 183                                                         /* load address */
 184 #define CONFIG_SYS_TEXT_BASE            0x80008000
 185
 186 /*
 187  * OMAP3 has 12 GP timers, they can be driven by the system clock
 188  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 189  * This rate is divided by a local divisor.
 190  */
 191 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 192 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 193
 194 /*
 195  * Physical Memory Map
 196  */
 197 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 198 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 199 #define PHYS_SDRAM_1_SIZE       (32 << 20)      /* at least 32 MiB */
 200 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 201
 202 /*
 203  * FLASH and environment organization
 204  */
 205
 206 /* **** PISMO SUPPORT *** */
 207 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 208 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 209
 210 /* Monitor at start of flash */
 211 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 212 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 213
 214 #define CONFIG_ENV_IS_IN_NAND           1
 215 #define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
 216 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 217
 218 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)
 219 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 220 #define CONFIG_ENV_ADDR                 CONFIG_ENV_OFFSET
 221
 222 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 223 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 224 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 225 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 226                                          CONFIG_SYS_INIT_RAM_SIZE - \
 227                                          GENERATED_GBL_DATA_SIZE)
 228
 229 #define CONFIG_OMAP3_SPI
 230
 231 /*
 232  * USB
 233  *
 234  * Currently only EHCI is enabled, the MUSB OTG controller
 235  * is not enabled.
 236  */
 237
 238 /* USB EHCI */
 239 #define CONFIG_USB_EHCI
 240 #define CONFIG_USB_EHCI_OMAP
 241 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO        162
 242
 243 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 244 #define CONFIG_USB_HOST_ETHER
 245 #define CONFIG_USB_ETHER_SMSC95XX
 246
 247 #define CONFIG_USB_ETHER
 248 #define CONFIG_USB_ETHER_RNDIS
 249
 250 /* Defines for SPL */
 251 #define CONFIG_SPL_FRAMEWORK
 252 #define CONFIG_SPL_NAND_SIMPLE
 253
 254 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 255 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 256
 257 #define CONFIG_SPL_BOARD_INIT
 258 #define CONFIG_SPL_NAND_BASE
 259 #define CONFIG_SPL_NAND_DRIVERS
 260 #define CONFIG_SPL_NAND_ECC
 261 #define CONFIG_SPL_OMAP3_ID_NAND
 262 #define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/u-boot-spl.lds"
 263
 264 /* NAND boot config */
 265 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 266 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 267 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 268 #define CONFIG_SYS_NAND_OOBSIZE         64
 269 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 270 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 271 /*
 272  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 273  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 274  */
 275 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
 276                                          10, 11, 12, 13 }
 277 #define CONFIG_SYS_NAND_ECCSIZE         512
 278 #define CONFIG_SYS_NAND_ECCBYTES        3
 279 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 280
 281 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 282 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 283
 284 #define CONFIG_SPL_TEXT_BASE            0x40200800
 285 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 286                                          CONFIG_SPL_TEXT_BASE)
 287
 288 /*
 289  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 290  * older x-loader implementations. And move the BSS area so that it
 291  * doesn't overlap with TEXT_BASE.
 292  */
 293 #define CONFIG_SYS_TEXT_BASE            0x80008000
 294 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 295 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 296
 297 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 298 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 299
 300 #endif /* __CONFIG_H */